HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 402
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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10. 8-Bit Timers
10.4.4
Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: CMFA and CMFB in
8TCSR are set to 1 by the compare match signal output when the TCOR and 8TCNT values
match. The compare match signal is generated in the last state of the match (when the matched
8TCNT count value is updated). Therefore, after the 8TCNT and TCOR values match, the
compare match signal is not generated until an incrementing clock pulse is generated. Figure 10.14
shows the timing in this case.
Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture
signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB.
Figure 10.15 shows the timing in this case.
Rev.5.00 Sep. 12, 2007 Page 372 of 764
REJ09B0396-0500
Compare match signal
Input capture signal
TCORB
8TCNT
Timing of Status Flag Setting
8TCNT
TCOR
CMFB
CMF
Figure 10.14 CMF Flag Setting Timing when Compare Match Occurs
Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs
φ
φ
N
N
N
N
N + 1
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