HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 309
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B. When pins are used for TPC output, the corresponding
PBDDR bits must also be set.
Bit
Initial value
Read/Write
When a pin in port B becomes an output port if the corresponding PBDDR bit is set to 1, and an
input port if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. When transition is made to software standby mode while a PBDDR
bit is set to 1, the corresponding pin maintains its output state.
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data
for pins port B. When port B functions as an output port, the value of this register is output. When
a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned.
When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read.
Bit
Initial value
Read/Write
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
PB DDR
PB
R/W
7
W
0
7
0
7
7
PB DDR
R/W
PB
6
W
0
6
0
6
6
PB DDR
PB
R/W
5
W
0
5
0
5
Port B data direction 7 to 0
These bits select input or output for port B pins
5
Port B data 7 to 0
These bits store data for port B pins
PB DDR
R/W
PB
4
W
0
4
0
4
4
PB DDR
Rev.5.00 Sep. 12, 2007 Page 279 of 764
R/W
PB
3
W
0
3
0
3
3
PB DDR
R/W
PB
2
W
0
2
0
2
2
PB DDR
R/W
PB
1
W
0
1
0
1
REJ09B0396-0500
1
PB DDR
8. I/O Ports
PB
R/W
0
W
0
0
0
0
0
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