EM250-RTR Ember, EM250-RTR Datasheet - Page 100

• Manufacturer Part Number: EM250-RTR
• Description: IC ZIGBEE SYSTEM-ON-CHIP 48-QFN
• Manufacturer: Ember
• Series: EM250r

Specifications of EM250-RTR

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: Home/Building Automation, Industrial Control and Monitoring
• Power - Output: 3dBm
• Sensitivity: -97dBm
• Voltage - Supply: 2 V ~ 3.6 V
• Current - Receiving: 35.5mA
• Current - Transmitting: 33mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 5kB SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• For Use With: 636-1009 - PROGRAMMER USB FLASH EM250/260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate - Maximum: -
• Other names: 636-1000-2

EM250
ADC_DATA [0x4900]
5.6
100
ADC_DATA
Event Manager
0-R
0-R
15
7
120-0082-000I
The XAP2b core supports one IRQ and one wake-up input; however, the EM250 contains an advanced Event
Manager that takes IRQ and WAKE_UP signals from a variety of internal and external sources and provides
them to the XAP2b. The Event Manager allows for each event to be separately masked and cleared by the
CPU, and ensures that all events are serviced properly and promptly.
Event sources include:
All interrupt source signals (except level-triggered GPIO interrupt signals) are momentary pulses that are
guaranteed to be a single cycle of the main 12MHz clock. They will synchronously set the corresponding inter-
rupt source bit(s) within a set of hierarchically organized interrupt source register(s). The interrupt controller
merges these hierarchical interrupt sources into the single interrupt input to the CPU. Table 37 illustrates the
enable and configuration status of each event within the EM250.
Event
Interrupt pin to CPU
Top: INT_FLAG
2
The hierarchy has two levels of interrupt source and associated mask registers for fine control of interrupt
processing. The top-level
EM250. The second level is a set of
sub-function within their respective module. Some modules, like ADC, have no second level. For a top-level
event to actually interrupt the CPU, it must be enabled in the top-level
must additionally be enabled in their respective second-level
To clear (acknowledge) an interrupt, software must write a 1 into the corresponding bit of the interrupt's low-
est level
level, software must write a 1 into the
RXVALID second-level interrupt, software must write a 1 into the
INT_SC1FLAG
INT_FLAG
The interrupt source register bits are designed to remain set if the event reoccurs at the same moment the bit
is being cleared to acknowledge a prior occurrence.
nd
0-R
0-R
14
6
: INT_periphFLAG
[15:0]
Timer events
GPIO events
SC1 and SC2 events
ADC
System-mode sources (MAC, Watchdog, etc.)
INT_periphFLAG
register would remain set, representing the “or” of all second-level-enabled SC1 interrupt events.
register. If there were other enabled SC1 interrupts pending, the top-level
ADC sample value. Refer to Table 33 and Table 35 for details.
0-R
0-R
13
5
INT_FLAG
register. For example, to acknowledge an ADC interrupt, which has no second
Table 37. Event Enable and Configuration Status
0-R
0-R
Configuration
INT_EN
INT_CFG
INT_periphCFG
12
4
INT_periphFLAG
and
ADC_DATA
ADC_DATA
INT_ADC
INT_CFG
bit of the top-level
registers have one bit per major functional module of the
0-R
0-R
11
3
and
INT_periphCFG
INT_periphCFG
INT_SCRXVAL
0-R
0-R
10
INT_FLAG
2
INT_CFG
registers that each have one bit per
registers.
register. To acknowledge a SC1
bit of the second-level
register. Second-level events
0-R
0-R
9
1
INT_SC1
bit in the
0-R
0-R
8
0