SLRC40001T/OFE,112 NXP Semiconductors, SLRC40001T/OFE,112 Datasheet - Page 71

• Manufacturer Part Number: SLRC40001T/OFE,112
• Description: IC I.CODE SLRC400 READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of SLRC40001T/OFE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1124-5; 935269551112; SLRC400; SLRC41TOFED

Philips Semiconductors
I•CODE Reader IC
8.2
8.2.1
The SL RC400 informs the µ-Processor about the interrupt request source by setting the according bit in the
InterruptRq Register. The relevance of each interrupt request bit as source for an interrupt may be masked
with the interrupt enable bits of the InterruptEn Register.
If any interrupt request flag is set to 1 (showing that an interrupt request is pending) and the corresponding
interrupt enable flag is set the status flag IRq in the PrimaryStatus Register is set to 1. Furthermore, different
interrupt sources can be set active simultaneously. Therefore, all interrupt request bits are ‘OR’ed and
connected to the flag IRq and forwarded to pin IRQ.
8.2.2
The interrupt request bits are set automatically by the internal state machines of the SL RC400. Additionally
the µ-Processor has access in order to set or to clear them.
A special implementation of the InterruptRq and the InterruptEn Register allows to change the status of a
single bit without influencing the other ones. If a specific interrupt register shall be set to one, the bit SetIxx
has to be set to 1 and simultaneously the specific bit has to be set to 1 too. Vice versa, if a specific interrupt
flag shall be cleared, a zero has to be written to the SetIxx and simultaneously the specific address of the
interrupt register has to be set to 1. If a bit content shall not be changed during the setting or clearing phase
a zero has to be written to the specific bit location.
Example: writing 3F
other bits are set to 1. Writing 81
8.3
The logic level of the status flag IRq is visible at pin IRQ. In addition, the signal on pin IRQ may be controlled
by the following bits of the IRQPinConfig Register:
•
•
Note: During the Reset Phase (see 11.2) IRQInv is set 1 and IRQPushPull to 0. This results in a high
impedance at pin IRQ.
InterruptEn
InterruptRq
Register
IRQInv: if set to 0, the signal on pin IRQ is equal to the logic level of bit IRq.
If set to 1, the signal on pin IRQ is inverted with respect to bit IRq.
IRQPushPull: if set to 1, pin IRQ has standard CMOS output characteristics
otherwise it is an open drain output and an external resistor is necessary to achieve a HIGH level at this
pin.
Implementation of Interrupt Request Handling
Configuration of Pin IRQ
CONTROLLING INTERRUPTS AND THEIR STATUS
ACCESSING THE INTERRUPT REGISTERS
SetIEn
SetIRq
Bit 7
hex
to the InterruptRq Register clears all bits as SetIRq in this case is set to 0 and all
Bit 6
RFU
RFU
hex
sets bit LoAlertIRq to 1 and leaves all other bits untouched.
Table 8-2: Interrupt Control Registers
TimerIRq
TimerIEn
Bit 5
TxIEn
TxIRq
Bit 4
71
RxIEn
RxIRq
Bit 3
Product Specification Rev. 3.1 August 2004
IdleIRq
IdleIEn
Bit 2
HiAlertIRq
HiAlertIEn
Bit 1
SL RC400
LoAlertIEn
LoAlertIRq
Bit 0