M0516ZAN Nuvoton Technology Corporation of America, M0516ZAN Datasheet - Page 146

• Manufacturer Part Number: M0516ZAN
• Description: IC MCU 32BIT 64KB FLASH 33QFN
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M0516ZAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 33-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Port0-4 Data Output Write Mask (Px _DMASK)
Register
P0_DMASK GP_BA+0x00C R/W
P1_DMASK GP_BA+0x04C R/W
P2_DMASK GP_BA+0x08C R/W
P3_DMASK GP_BA+0x0CC R/W
P4_DMASK GP_BA+0x10C R/W
Bits
[31:8]
[n]
31
23
15
7
NuMicro M051
Offset
Descriptions
Reserved
DMASK[n]
30
22
14
6
R/W
Reserved
Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set
the DMASK bit[n] to “1”, the corresponding Px_DOUTn bit is protected. The write signal is
masked, write data to the protect bit is ignored
0 = The corresponding Px_DOUT[n] bit is not masked
1 = The corresponding Px_DOUT[n] bit is masked
x=0~4, n = 0~7
29
21
13
5
™
Description
P0 Data Output Write Mask
P1 Data Output Write Mask
P2 Data Output Write Mask
P3 Data Output Write Mask
P4 Data Output Write Mask
Series Technical Reference Manual
28
20
12
4
DMASK[7:0]
- 146 -
Reserved
Reserved
Reserved
27
19
11
3
Publication Release Date: Sep 14, 2010
26
18
10
2
25
17
9
1
Revision V1.2
Reset Value
0xXXXX_XX00
0xXXXX_XX00
0xXXXX_XX00
0xXXXX_XX00
0xXXXX_XX00
24
16
8
0