DS92LV2421SQE/NOPB National Semiconductor, DS92LV2421SQE/NOPB Datasheet
DS92LV2421SQE/NOPB
Specifications of DS92LV2421SQE/NOPB
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DS92LV2421SQE/NOPB Summary of contents
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... DS92LV2422 is offered in a 60-pin LLP package. Both de- vices operate over the full industrial temperature range of -40° +85°C. Applications Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS92LV2421/DS92LV2422 Features ■ 24–bit data, 3–bit control, 10 – 75 MHz clock ■ ...
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Block Diagrams Ordering Information NSID Package Description DS92LV2421SQE 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS92LV2421SQ 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS92LV2421SQX 48–pin LLP, 7.0 X 7.0 X 0.8 mm, ...
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DS92LV2421 Pin Diagram DS92LV2421 Serializer Pin Descriptions Pin Name Pin # I/O, Type LVCMOS Parallel Interface DI[7:0] 34, 33, 32, 29, I, LVCMOS 28, 27, 26 pull-down DI[15:8] 42, 41, 40, 39, I, LVCMOS 38, 37, 36, 35 ...
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Pin Name Pin # I/O, Type CLKIN 10 I, LVCMOS w/ pull-down Control and Configuration PDB 21 I, LVCMOS w/ pull-down VODSEL 24 I, LVCMOS w/ pull-down De-Emph 23 I, Analog w/ pull-up RFB 11 I, LVCMOS w/ pull-down CONFIG ...
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DS92LV2422 Pin Diagram DS92LV2422 Deserializer Pin Descriptions Pin Name Pin # I/O, Type LVCMOS Parallel Interface DO[7:0] 33, 34, 35, I, STRAP, 36, 37, 39, O, LVCMOS 40, 41 DO[15:8] 20, 21, 22, I, STRAP, 23, 25, 26, O, LVCMOS ...
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Pin Name Pin # I/O, Type CO1 6 O, LVCMOS Control Signal Output CO2 8 O, LVCMOS Control Signal Output CO3 7 O, LVCMOS Control Signal Output CLKOUT 5 O, LVCMOS Pixel Clock Output LOCK 32 O, LVCMOS LOCK Status ...
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Pin Name Pin # I/O, Type OS_DATA 14 [DO19] STRAP I, LVCMOS w/ pull-down OP_LOW 42 [PASS] STRAP I, LVCMOS w/ pull-down OSS_SEL 17 [DO18] STRAP I, LVCMOS w/ pull-down RFB 18 [DO17] STRAP I, LVCMOS w/ pull-down EQ[3:0] 20 ...
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Pin Name Pin # I/O, Type NC 1, 15, 16, 30, 31, 45, 46, 60 Channel-Link II — CML Serial Interface RIN CML RIN CML CMF 51 I, Analog ROUT CML ROUT ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO LVCMOS I/O Voltage −0.3V to (VDDIO + 0.3V) Receiver Input Voltage Driver Output Voltage ...
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Symbol Parameter CML DRIVER DC SPECIFICATIONS V Differential Output Voltage OD Differential Output Voltage V ODp-p (DOUT+) – (DOUT-) ΔV Output Voltage Unbalance OD Offset Voltage – Single-ended & B, Figure 1 Offset Voltage Unbalance ...
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Symbol Parameter 1.8 V I/O LVCMOS DC SPECIFICATIONS – High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN V High Level Output Voltage OH V Low Level Output Voltage OL Output Short ...
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Recommended Serializer Timing for CLKIN Requirements Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Transmit Input CLKIN Period TCP t Transmit Input CLKIN High TCIH Time t Transmit Input CLKIN Low Time TCIL t CLKIN ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t CLK Output Period RCP t CLK Output Duty Cycle RDC t LVCMOS CLH Low-to-High Transition Time, Figure 10 t LVCMOS CHL High-to-Low Transition Time, ...
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Symbol Parameter SSCG Mode f Spread Spectrum DEV Clocking Deviation Frequency f Spread Spectrum MOD Clocking Modulation Frequency Recommended Timing for the Serial Control Bus Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter f SCL Clock ...
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DC and AC Serial Control Bus Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis SDA ...
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FIGURE 4. Serializer Input CLKIN Waveform and Set and Hold Times www.national.com FIGURE 2. Serializer Output Waveforms FIGURE 3. Serializer Output Transition Times FIGURE 5. Serializer Lock Time 16 30110130 30110147 30110131 30110148 ...
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FIGURE 6. Serializer Disable Time FIGURE 7. Serializer Latency Delay FIGURE 8. Serializer Output Jitter 17 30110149 30110110 30110150 www.national.com ...
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FIGURE 9. Checkerboard Data Pattern FIGURE 10. Deserializer LVCMOS Transition Times FIGURE 11. Deserializer Delay – Latency FIGURE 12. Deserializer Disable Time (OSS_SEL = 0) 18 30110132 30110105 30110111 30110113 ...
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FIGURE 13. Deserializer PLL Lock Times and PDB TRI-STATE™ Delay FIGURE 14. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off FIGURE 15. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On 19 30110114 ...
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FIGURE 16. Receiver Input Jitter Tolerance FIGURE 17. BIST PASS Waveform FIGURE 18. Serial Control Bus Timing Diagram 20 30110116 30110152 30110136 ...
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Functional Description The DS92LV2421 / DS92LV2422 chipset transmits and re- ceives 24-bits of data and 3 control signals over a single serial CML pair operating at 280 Mbps to 2.1 Gbps. The serial stream also contains an embedded clock, video ...
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This encoding process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges from the parallel clock frequency to the nyquist rate. For example, ...
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DESERIALIZER Functional Description The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal check for the chipset Built In Self Test (BIST) mode. The device can be configured via external ...
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TABLE 6. SSCG Configuration (LF_MODE = L) — Des Output SSC[3:0] Inputs LF_MODE = L ( MHz) SSC3 SSC2 ...
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When the serial stream starts again, the Des will then lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus Control Registers values are ...
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FIGURE 22. Des Outputs with Output State Select High (OSS_SEL = H) OSC_SEL[2:0] INPUTS OSC_SEL2 OSC_SEL1 www.national.com TABLE 10. OSC_SEL (Oscillator) Configuration CLKOUT Oscillator ...
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FIGURE 23. Des Outputs with Output State High and CLK Output Oscillator Option Enabled Des — OP_LOW — Optional The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output LOW state. When the ...
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Des — Clock Edge Select (RFB) The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising edge of the CLKOUT. If RFB is Low, data is strobed ...
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Des — Control Signal Filter — Optional The deserializer provides an optional Control Signal (C3, C2, C1) filter that monitors the three control signals and eliminates any pulses or glitches that are parallel clock periods wide. Control ...
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Optional Serial Bus Control The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by ...
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If the Serial Bus is not required, the three pins may be left open (NC). TABLE 11. ID[x] Resistor Value – DS92LV2421 Ser Resistor Address 7'b RID kΩ 0.47 7b' 110 1001 (h'69) 8b' 1101 0010 (h'D2) 2.7 7b' 110 ...
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TABLE 13. SERIALIZER — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Ser Config 1 3 Device ID 6 De-Emphasis 7:5 Control 3:0 www.national.com R/W Defa Function ult (bin) 7 R/W ...
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TABLE 14. DESERIALIZER — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Des Config 3 Slave Des Features ...
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ADD ADD Register Name Bit(s) (dec) (hex Des Features 2 7:5 3 ROUT Config 6:0 www.national.com R/W Defa Function ult (bin) R/W 000 EQ Gain 4 R Enable R/W 0000 SSC 7 R/W 0 ...
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Applications Information DISPLAY APPLICATION The DS92LV2421/DS92LV2422 chipset is intended for inter- face between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888 RGB888 ap- plication, 24 color bits (D[23:0), Pixel Clock (CLKIN) and ...
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Figure 33 shows a typical application of the DS92LV2422 Des in Pin/STRAP control mode 24-bit Application. The LVDS in- puts utilize 100 nF coupling capacitors to the line and the receiver provides internal termination. Bypass capacitors are placed near the ...
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POWER UP REQUIREMENTS AND PDB PIN The VDD (V and V ) supply ramp should be faster than DDn DDIO 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed ...
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Physical Dimensions 48–pin LLP Package (7 7 0.8 mm, 0.5 mm pitch) 60–pin LLP Package (9 9 0.8 mm, 0.5 mm pitch) www.national.com inches (millimeters) unless otherwise noted NS Package Number SQA48A ...
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Notes 39 www.national.com ...
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