DS92LV2421SQE/NOPB National Semiconductor, DS92LV2421SQE/NOPB Datasheet - Page 25

• Manufacturer Part Number: DS92LV2421SQE/NOPB
• Description: IC SER/DESER 10-75MHZ 24B 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2421SQE/NOPB

• Serdes Function: Serialiser
• Ic Input Type: LVCMOS
• Ic Output Type: CML
• No. Of Inputs: 1
• No. Of Outputs: 1
• Supply Voltage Range: 1.71V To 1.89V
• Driver Case Style: LLP
• No. Of Pins: 48
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV2421SQE/NOPBTR

the embedded clock bits are not present. When the serial
stream starts again, the Des will then lock to the incoming
signal and recover the data. Note – in STOP STREAM
SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
Des — CLOCK-DATA RECOVERY STATUS FLAG (LOCK)
and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to
the serial input and LOCK goes from TRI-STATE to LOW
(depending on the value of the OSS_SEL setting). After the
DS92LV2422 completes its lock sequence to the input serial
data, the LOCK output is driven HIGH, indicating valid data
and clock recovered from the serial input is available on the
* NOTE — Absent and OSC_SEL
Serial
Active
Static
Static
Input
Embedded CLK
X
X
INPUTS
NOTE *
Present
INPUTS
PDB
H
H
H
FIGURE 21. Des Outputs with Output State Select Low (OSS_SEL = L)
L
L
TABLE 8. OSS_SEL and PDB Configuration — Des Outputs
≠
000
CLKOUT
Toggling
TABLE 9. OSC (Oscillator) Mode — Des Output
Output
OSC
OSS_SEL
H
H
X
L
L
CLKOUT
Active
25
Z
Z
L
L
DO[23:0]/CO1/CO2/CO3
parallel bus and clock outputs. The CLKOUT output is held at
its current state at the change from OSC_CLK (if this is en-
abled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK
is driven Low and the state of the outputs are based on the
OSS_SEL setting (STRAP PIN configuration or register).
Des — Oscillator Output — Optional
The Des provides an optional clock output when the input
clock (serial stream) has been lost. This is based on an inter-
nal oscillator. The frequency of the oscillator may be selected.
This feature may be controlled by the external pin or by reg-
ister. See
Active
DO[23:0], CO1,
OUTPUTS
L
CO2, CO3
Table 9
Active
Z
L
Z
L
OUTPUTS
and
Table
10.
LOCK
H
Z
L
L
L
LOCK
H
L
PASS
www.national.com
H
H
H
H
Z
PASS
30110140
H
H