LFXP3C-3QN208C Lattice, LFXP3C-3QN208C Datasheet - Page 14

• Manufacturer Part Number: LFXP3C-3QN208C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTS 136 I/O
• Manufacturer: Lattice

Specifications of LFXP3C-3QN208C

• Number Of Macrocells: 3000
• Maximum Operating Frequency: 320 MHz
• Number Of Programmable I/os: 136
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-12 illustrates
the DCS Block Macro.
Figure 2-12. DCS Block Primitive
CLK0
CLK1
DCS
DCSOUT
SEL
Figure 2-13 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-13. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
sysMEM Memory
The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of
a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
2-11