PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 28

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

10.0
10.1
10.2
Datasheet
28
Security
J3-65nm device offer both hardware and software security features. Block lock
operations, PRs and VPEN allow users to implement various levels of data protection.
Normal Block Locking
J3-65nm has the unique capability of Flexible Block Locking (locked blocks remain
locked upon reset or power cycle): All blocks are unlocked at Numonyx factory. Blocks
can be locked individually by issuing the Set Block Lock Bit command sequence to any
address within a block. Once locked, blocks remain locked when power is removed, or
when the device is reset (see
page
All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits
command sequence to any device address. Locked blocks cannot be erased or
programmed.
After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup
command, the device’s read mode is automatically changed to Read Status Register
mode. After issuing the confirm command, completion of the operation is indicated by
STS (in RY/BY# mode) going high and SR.7 = 1.
Blocks cannot be locked or unlocked while programming or erasing, or while the device
is suspended. Reliable block lock and unlock operations occur only when V
are valid. When V
When the set lock-bit operation is complete, SR.4 should be checked for any error.
When the clear lock-bit operation is complete, SR.5 should be checked for any error.
Errors bits must be cleared using the Clear Status Register command.
Block lock-bit status can be determined by first issuing the Read Device Information
command, and then reading from <block base address> + 02h. DQ0 indicates the lock
status of the addressed block (0 = unlocked, 1 = locked).
Configurable Block Locking
One of the unique new features on the J3-65nm,which did not exist on the previous
generations of this product family, is the ability to protect and/or secure the user’s
system by offering multiple level of securities: Non-Volatile Temporary; Non-Volatile
Semi-Permanent or Non-Volatile Permanent. For additional information and collateral
request, please contact your filed representative .
60).
Table 8
PEN
≤ V
summarizes the command bus-cycles.
PENLK
, block lock-bits cannot be changed.
Figure 20, “Block Lock Operations Flowchart” on
Numonyx™ StrataFlash
®
Embedded Memory (J3-65nm)
CC
December 2008
and V
319942-02
PEN