PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 36

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

12.2
Table 16: Power and Reset
Figure 7:
Datasheet
36
Notes:
1.
2.
3.
4.
5.
6.
7.
Num
P1
P2
P3
(A) Reset during
(B) Reset during
(C) Reset during
(D) VCC Power-up to
t
t
t
read mode
program or block erase
P1 ≤ P2
program or block erase
P1 ≥ P2
RST# high
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
Not applicable if RP# is tied to VCC.
Sampled, but not 100% tested.
When RP# is tied to the VCC supply, device will not be ready until t
When RP# is tied to the VCCQ supply, device will not be ready until t
Reset completes within t
Symbol
PLPH
PLRH
VCCPH
Reset Operation Waveforms
Reset Specifications
Asserting RP# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RP# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RP# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
RP# pulse width low
RP# low to device reset during erase
RP# low to device reset during program
VCC Power valid to RP# de-assertion (high)
PLPH
PLPH
if RP# is asserted while no erase or program operation is executing.
is < t
Parameter
PLPH
Min, but this is not guaranteed.
RST# [P]
RST# [P]
RST# [P]
V
CC
V
V
V
V
V
V
V
0V
CC
IH
IH
IH
IL
IL
IL
Numonyx™ StrataFlash
VCCPH
VCCPH
Min
100
300
-
-
after VCC ≥ V
after VCC ≥ V
P1
P2
P2
P3
Complete
Max
Abort
®
25
25
-
-
Complete
CCMIN
Embedded Memory (J3-65nm)
Abort
CCMIN
.
.
Unit
ns
µs
R5
R5
December 2008
R5
319942-02
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
Notes