PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 35

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

Numonyx™ StrataFlash
12.0
12.1
12.1.1
Table 15: Power-Up/Down Sequence
Note:
December 2008
319942-02
Power Supply
V
V
Voltage
V
CCQ(min)
PEN(min)
CC(min)
Power and Reset Specifications
Power-Up and Power-Down
Power supply sequencing is not required if VPEN is connected to VCC or VCCQ.
Otherwise VCC and VCCQ should attain their minimum operating voltage before
applying VPEN.
Power supply transitions should only occur when RP# is low. This protects the device
from accidental programming or erasure during power transitions.
Power-Up/Down Characteristics
To prevent conditions that could result in spurious program or erase operations, several
valid power-up/power-down sequences shown in
voltage characteristics refer to
minimum voltage range before applying/removing the next supply voltage.
Power supplies connected or sequenced together.
Device inputs must not be driven until all supply voltages reach their minimum range.
RP# should be low during power transitions.
®
2nd
3rd
1st
Embedded Memory (J3-65nm)
Power-Up Sequence
2nd
1st
†
1st
2nd
†
Table
Sequencing not
required
20. Note that each power supply must reach its
†
2nd
3rd
1st
Table 15
Power-Down Sequence
1st
2nd
are recommended. For DC
†
2nd
1st
†
Sequencing not
required
Datasheet
†
35