PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 33

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

Numonyx™ StrataFlash
11.3.3
Figure 6:
Note:
Table 13: Word-Wide Protection Register Addressing
December 2008
319942-02
Note:
LOCK
Word
A0 is not used in x16 mode when accessing the protection register map. See
A0 is used, see
0
1
2
3
4
5
6
7
All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.)
Protection Register Memory Map
Protection Register Addressing” on page 33
Addressing” on page
page
address space will result in a Status Register error (SR.4 will be set). Attempting to
program a locked PR segment will result in a Status Register error (SR.4 and SR.1 will
be set).
Locking the OTP Protection Register
The user-programmable segment of the PR is lockable by programming Bit 1 of the
Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the
Numonyx factory to protect the unique device number. Bit 1 is set using the Protection
Program command to program “0xFFFD” to the PLR. After these bits have been
programmed, no further changes can be made to the values stored in the Protection
Register. Protection Program commands to a locked section will result in a Status
Register error (SR.4 and SR.1 will be set). The PR lockout state is not reversible.
Table 14
Factory
Factory
Factory
Factory
62. Any attempt to address Protection Program commands outside the defined PR
®
Both
User
User
User
User
Use
Embedded Memory (J3-65nm)
Address
Word
for x8 addressing.
0x88
0x85
0x84
0x81
0x80
A8
1
1
1
1
1
1
1
1
1
15 14 13 12 11 10 9
34. See
128-Bit Protection Register 0
A[24:1]: 256 Mbit
A[23:1]: 128 Mbit
(Factory-Programmed)
A7
(User-Programmable)
0
0
0
0
0
0
0
0
0
Figure 22, “OTP Register Programming Flowchart” on
64-bit Segment
64-bit Segment
Lock Register 0
8
7
A6
0
0
0
0
0
0
0
0
0
6
5
4
or
A[22:1]: 64 Mbit
A[21:1]: 32 Mbit
3
A5
2
0
0
0
0
0
0
0
0
0
Table 14, “Byte-Wide Protection Register
1
0
Table 13
A4
0
0
0
0
0
0
0
0
1
for x16 addressing. In x8 mode
A3
0
0
0
0
1
1
1
1
0
A2
0
0
1
1
0
0
1
1
0
Datasheet
A1
0
1
0
1
0
1
0
1
0
33