PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 41

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

Numonyx™ StrataFlash
15.0
Figure 8:
Figure 9:
Note:
15.1
Figure 10: AC Input/Output Reference Waveform
Note:
December 2008
319942-02
Address
Data - Read
Data - Write
Chip Enable (CE)
Output Enable (OE#)
Write Enable (WE#)
BYTE#
Reset (RP#)
STS
VPEN
AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input
rise and fall times (10% to 90%) < 5 ns. Worst-case speed occurs at VCC = VCCMin.
V
0V
CCQ
Signal
Timing Signal Naming Convention
Timing Signal Name Decoder
AC characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention
Exceptions to this convention include t
refers to the aggregate initial-access delay as determined by t
(whichever is satisfied last) of the flash device. t
data sheet, and is the address-to-data delay for subsequent page-mode reads.
AC Test Conditions
Input V
®
Embedded Memory (J3-65nm)
Source Signal
Source State
CCQ
/2
E
W
A
Q
D
G
F
P
R
V
t
Code
E
Test Points
L Q V
High
Low
High-Z
Low-Z
Valid
Invalid
ACC
and t
APA
APA
State
Target State
Target Signal
. t
ACC
is specified in the flash device’s
is a generic timing symbol that
V
CCQ
AVQV
/2 Output
, t
H
L
Z
X
V
I
ELQV
IO_REF.WMF
, and t
Code
GLQV
Datasheet
41