LAN8187-JT SMSC, LAN8187-JT Datasheet - Page 56

• Manufacturer Part Number: LAN8187-JT
• Description: Ethernet ICs HiPerfrm Ethrnt PHY
• Manufacturer: SMSC
• Type: MII/RMII Ethernet Transceiverr

Specifications of LAN8187-JT

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 802.3ab
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (03-04-11)
5.4.9.2
MODE[2:0]
000
001
010
100
101
011
110
111
PHY application, this ensures that the scramblers are out of synchronization and disperses the
electromagnetic radiation across the frequency spectrum.
Mode Bus – MODE[2:0]
The MODE[2:0] bus controls the configuration of the 10/100 digital block. When the nRST pin is de-
asserted, the register bit values are loaded according to the MODE[2:0] pins. The 10/100 digital block
is then configured by the register bit values. When a soft reset occurs (bit 0.15) as described in
Table
MODE[2:0] pins have no affect.
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
100Base-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
Power Down mode. In this mode the PHY wake-up
in Power-Down mode. The PHY cannot be used
when the MODE[2:0] bits are set to this mode. To
exit this mode, the MODE[2:0] bits must be
configured to some other value and a soft reset
must be issued.
All capable. Auto-negotiation enabled.
5.30, the configuration of the 10/100 digital block is controlled by the register bit values, and the
MODE DEFINITIONS
Table 5.48 MODE[2:0] Bus
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
DATASHEET
56
DEFAULT REGISTER BIT VALUES
REGISTER 0
[13,12,10,8]
X10X
0000
0001
1000
1001
1100
1100
N/A
SMSC LAN8187/LAN8187i
REGISTER 4
[8,7,6,5]
0100
0100
1111
N/A
N/A
N/A
N/A
N/A
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