MT48LC8M16A2P-75 IT:G TR Micron Technology Inc, MT48LC8M16A2P-75 IT:G TR Datasheet - Page 20

• Manufacturer Part Number: MT48LC8M16A2P-75 IT:G TR
• Description: DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M16A2P-75 IT:G TR

• Density: 128 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Organization: 8Mx16
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1099-2

Table 6:
Figure 8:
Operating Mode
Write Burst Mode
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
CAS Latency
CAS Latency
COMMAND
COMMAND
The normal operating mode is selected by setting M7 and M8 to 0; the other combina-
tions of values for M7 and M8 are reserved for future use and/or test modes. The
programmed BL applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, the BL programmed via M0–M2 applies both to read and write bursts;
when M9 = 1, the programmed BL applies to read bursts, but write accesses are single-
location (nonburst) accesses.
CLK
CLK
DQ
DQ
Speed
-6A
-7E
-75
READ
READ
T0
T0
CL = 2
NOP
NOP
T1
T1
20
t
t AC
LZ
CL = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Allowable Operating Frequency (MHz)
CL = 2
≤ 133
≤ 100
T2
NOP
T2
NOP
–
t
t AC
LZ
D
t OH
OUT
128Mb: x4, x8, x16 SDRAM
T3
T3
NOP
D
t OH
Functional Description
OUT
DON’T CARE
UNDEFINED
©1999 Micron Technology, Inc. All rights reserved.
T4
CL = 3
≤ 167
≤ 143
≤ 133