MT48LC8M16A2P-75 IT:G TR Micron Technology Inc, MT48LC8M16A2P-75 IT:G TR Datasheet - Page 54

• Manufacturer Part Number: MT48LC8M16A2P-75 IT:G TR
• Description: DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M16A2P-75 IT:G TR

• Density: 128 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Organization: 8Mx16
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1099-2

Figure 38:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMH
COMMAND
A0–A9, A11
Precharge all
DQM /
BA0, BA1
active banks
CKE
CLK
A10
DQ
Power-Down Mode
t CMS
High-Z
t CKS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
Notes:
BANK(S)
T0
t CKH
t CMH
t AH
1. Violating refresh requirements during power-down may result in a loss of data.
Two clock cycles
All banks idle, enter
power-down mode
t CK
T1
NOP
t CKS
t CL
T2
NOP
Input buffers gated off while in
power-down mode
t CH
54
Exit power-down mode
(
(
(
(
(
(
)
)
(
)
(
)
(
)
)
(
(
(
)
)
)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
)
)
(
)
(
(
(
(
(
(
(
)
)
(
)
(
)
(
)
(
)
(
)
)
(
)
)
)
)
)
(
(
)
)
)
128Mb: x4, x8, x16 SDRAM
t CKS
Tn + 1
NOP
All banks idle
©1999 Micron Technology, Inc. All rights reserved.
Timing Diagrams
Tn + 2
ACTIVE
ROW
ROW
BANK
DON’T CARE