TXC-03303-ARPQ Transwitch Corporation, TXC-03303-ARPQ Datasheet - Page 32

• Manufacturer Part Number: TXC-03303-ARPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03303-ARPQ

• Lead Free Status / RoHS Status: Compliant

MEMORY MAP DESCRIPTIONS
Address
00
Bit
7
6
5
4
3
2
1
Symbol
R3OOF
R3LOS
R3CKF
T3CKF
R3AIS
R3IDL
XR2
Receive DS3 Loss of Signal: A receive LOS alarm occurs when the
incoming DS3 data (DS3DR) is stuck low for more than 1022 clock cycles
(DS3CR). Recovery occurs when two or more ones are detected in the
incoming data bit stream. This bit position is unlatched.
Receive DS3 Out of Frame: A receive OOF alarm occurs when three out
of 16 F-bits are in error utilizing a sliding window of 16 bits, or one or more
M-bits are in error in two consecutive frames. Recovery occurs when the F
framing pattern of 1001 is detected, and the M framing pattern of 010 is
detected for two consecutive frames. Recovery takes approximately 0.95
milliseconds, worst case. This bit position is unlatched. An OOF also inhib-
its the performance counters (04H, 05H, 06H, 1BH, 22H, and 23H).
Receive AIS Alarm Indication Signal: The M13E detects DS3 AIS by six
methods. The method of detection that drives the R3AIS alarm is selected
by the states written to the three R3AISn bits in register 21H. This bit posi-
tion is unlatched. When the M13E is configured to detect one of the framed
AIS signals (selected via bits 4-2 of register 21H), the R3OOF (bit 6 of this
register) should be examined to ensure that the M13E is detecting DS3
frame.
Receive DS3 Idle Pattern Signal: A DS3 idle pattern signal has a valid M-
frame alignment channel, M-subframe alignment channel, and P-bit chan-
nel. The information bits are a 1100 sequence that starts with 11 after each
M-frame alignment, M-subframe alignment, X-bit, P-bit, and C-bit channels.
The C-bits (C7, C8, and C9) in M-subframe 3 are set to zero. A valid
received DS3 idle signal is detected when the M13 detects zeros for C7,
C8, and C9 in subframe 3 and the 1100 sequence. The M13E searches for
the 1100 pattern sequence on a per DS3 frame basis. The M13E can toler-
ate up to and including 5 errored 4-bit groups of the 1100 pattern per DS3
frame and still recognize the 1100 pattern as valid. If the M13E detects 6 or
more errored 4-bit groups of the 1100 pattern per DS3 frame the M13E will
exit the R3IDL state. This bit position is unlatched. A DS3 idle signal as
defined in ANSI T1.107a-1990 is being received by the M13E device if this
bit and bits 1 and 0 of this register are all set to 1.
Receive DS3 Clock Failure: A receive DS3 clock failure alarm occurs
when the receive clock (DS3CR) is stuck high or low for 30-100 DS3 clock
periods. Recovery occurs on the first clock transition. The demultiplexer
does not function when the receive clock is lost. The DS3CR pin is still
monitored for this alarm during DS3 line loopback (control bit 3LBK=1), so
that it may be necessary to set control bits 1TAIS1 and 1TAIS0 to 11 to pre-
vent AIS insertions into the receive DS1 data stream. This bit position is
unlatched.
Transmit DS3 Clock Failure: A transmit DS3 clock failure alarm occurs
when the transmit input clock (XCK) is stuck high or low for 30-100 DS3
clock periods. A failure causes the receive clock to become the transmit
clock. This permits the M13E microprocessor interface and multiplexer to
function. Recovery occurs when the first clock transition is detected.
Receive DS3 X-bit Number 2: This bit position indicates the receive state
of X2. This bit position is updated each frame.
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Description
Ed. 4, August 1998
TXC-03303
TXC-03303-MB
M13E