TXC-03303-ARPQ Transwitch Corporation, TXC-03303-ARPQ Datasheet - Page 34

• Manufacturer Part Number: TXC-03303-ARPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03303-ARPQ

• Lead Free Status / RoHS Status: Compliant

Address
02
03
Bit
7
6
5
4
3
2
1
0
7
M13MODE M13 Operating Mode: A one enables the M13E to operate in the M13
Symbol
LPTIME
TEST1
INVCK
CBIT1
3LBK
IDLB
IDLA
1INV
DS1 Idle Code Selection: Three DS1 idle codes are provided according to
the table given below. A selected idle code is common to all DS1 channels
selected. One or more transmitted DS1 channels is selected by writing a
one in IDLn register locations 10H, 11H, 12H, or 13H, provided register
location 1EH has not selected that DS1 channel for loopback.
Reserved for TranSwitch Testing Purposes: A zero must be written into
this bit position.
DS3 Line Loopback: A one disables the DS3 receive input and causes the
DS3 transmit output to be looped back as receive data. Transmit data is
provided at the output (DS3DT).
Receive Loop Timing: A one disables the transmit clock input (XCK), and
causes the DS3 receive clock to become the DS3 transmit clock. If the DS3
receive clock fails in this mode, the M13E switches over to the transmit
clock. The demultiplexer becomes inoperative, but the multiplexer and
microprocessor interface continue to function.
Invert DS1 Transmit Clocks: A one causes all transmit DS1 data inputs
(DTn) to be sampled on the falling edges of their respective DS1 clock
inputs (CTn). This is provided for back-to-back M13 operation.
Invert DS1 Transmit Data: A one causes the transmit data inputs for all
DS1 channels (DTn) to be inverted.
mode as specified in Bellcore TR-TSY-000009, and the ANSI T1.107-1988
standard. A zero enables the M13E to operate in the C-bit parity mode as
specified in the ANSI T1.107a-1990, supplement to ANSI T1.107-1988.
C-bit Number 1 State: This bit is updated each frame with the state of the
received C1 bit. The C1 bit is used to identify the DS3 application according
to the table given below:
In addition, any C-bit that is received as zero will index the C-bit Equals
Zero Counter (C1BZCNT) in 22H.
IDLB
X
0
1
IDLA
0
0
1
- 34 -
C1 Value
Random
All 1s
Quasi-Random Signal (2
suppression.
Framed Extended Super Frame (ESF) signal format
which consists of an S-bit pattern of 001011 in every
fourth signaling bit position, CRC-6 pattern, and ones
in the 64 kbit/s channels 1 through 24.
Unframed all ones signal (AIS).
Description
DS1 Idle Code Selected
Application
M13 format
C-bit parity format
20
- 1 QRS) including zero
Ed. 4, August 1998
TXC-03303
TXC-03303-MB
M13E