TXC-03303-ARPQ Transwitch Corporation, TXC-03303-ARPQ Datasheet - Page 35

• Manufacturer Part Number: TXC-03303-ARPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03303-ARPQ

• Lead Free Status / RoHS Status: Compliant

Address
(cont.)
03
04
05
06
6-0
7-0
7-0
7-0
Bit
DS2OOFn
Symbol
(n=7-1)
(n=7-0)
(n=7-0)
(n=7-0)
CPn
PPn
FBn
DS2 Out of Frame Alarm Indication: A one in bits 6-0 corresponds to an
out of frame alarm for the corresponding DS2 channel (7-1). A DS2 OOF
occurs when two out of four consecutive framing bits are in error. A DS2
OOF for a DS2 channel causes AIS to be inserted into its four DS1 chan-
nels when 1TAIS1, 1TAIS0 = 0, 0 or 0, 1. Recovery is based on searching
for the 0101 framing pattern. Framing is accomplished by starting at an
arbitrary point with the first received bit (0 or 1) and looking 49 bit positions
later for the bit of opposite sense. This search is performed for 12 bit posi-
tions simultaneously. Once the framing pattern is found, one more frame is
used to acquire alignment. Recovery takes approximately 6.8 milliseconds,
worst case average.
FEBE Performance Counter/DS3 F&M Bit Error Counter: This perfor-
mance counter counts the number of FEBEs received since the last read
cycle in the C-bit parity mode. A FEBE indication occurs when C10, C11, or
C12 is received equal to zero in a DS3 frame. The counter is protected from
overflow by stopping at the maximum count of 255 until read. The counter is
protected during the period of a microprocessor read cycle and when the
M13E is attempting to write to the counter. When this occurs, the incoming
error count indication is held until the counter is read and cleared. After-
wards, the counter increments. Only the indication of one error count is held
during the microprocessor read and the M13E write cycle. The counter is
also inhibited during DS3 loss of signal or out of frame times. This counter
is cleared when it is read by the microprocessor. In the M13 mode, this sat-
urating counter counts the number of DS3 F&M bits that have been
received in error. This counter is inhibited when a DS3 OOF occurs and
clears when read.
C-Bit Parity Performance/Number of Frames Counter: In the C-bit parity
mode, this counter counts the number of C-bit parity errors received since
the last read cycle. In the M13 mode, it counts the number of DS3 frames
since the last read cycle. The counter is protected during the period of a
microprocessor read cycle and when the M13E is attempting to write to the
counter. When this occurs, the incoming error count indication is held until
the counter is read and cleared. Afterwards, the counter increments. Only
the indication of one error count is held during the microprocessor read and
the M13E write cycle. The counter is inhibited during DS3 loss of signal or
out of frame times, and is cleared when it is read by the microprocessor.
P-Bit Parity Performance Counter: This counter counts the number of
P-bit parity errors received since the last read cycle. This performance
count is valid in either operating mode. The counter is protected during the
period of a microprocessor read cycle and when the M13E is attempting to
write to the counter. When this occurs, the incoming error count indication
is held until the counter is read and cleared. Afterward, the counter incre-
ments. Only the indication of one error count is held during the micropro-
cessor read and the M13E write cycle. The counter is also inhibited during
DS3 loss of signal or out of frame times. This counter is cleared when it is
read by the microprocessor.
- 35 -
Description
Ed. 4, August 1998
TXC-03303
TXC-03303-MB
M13E