TXC-03303-ARPQ Transwitch Corporation, TXC-03303-ARPQ Datasheet - Page 46

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TXC-03303-ARPQ

Manufacturer Part Number
TXC-03303-ARPQ
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-03303-ARPQ

Lead Free Status / RoHS Status
Compliant
Address
(cont.)
21
22
23
7-0
7-0
Bit
1
0
Symbol
T3AIS1
T3AIS0
(n=7-0)
(n=7-0)
C1BZn
MEn
Transmit DS3 AIS Selection: A DS3 AIS may be generated in one of four
ways. The following table selects the DS3 AIS generation mechanism:
C1 Bit Zero Counter: An 8-bit saturating counter that counts the number of
C1 bits equal to zero in both the C-bit parity mode and M13 mode. In the
M13 mode the contents of this counter should be disregarded. The counter
is inhibited when DS3 loss of signal or out of frame occurs. The counter is
cleared when it is read by the microprocessor.
DS3 M-bits in Error Counter: An 8-bit saturating counter that counts the
number of M-bits that are in error since the last read cycle. The counter is
inhibited when DS3 loss of signal or out of frame occurs. The counter is
cleared when it is read by the microprocessor.
Note: Set these bits to 0 when transmitting DS3 idle (see T3IDL in register 01H).
T3AIS1
0
0
1
1
T3AIS0
- 46 -
0
1
0
1
Transmit DS3 AIS Selection
ANSI defined AIS generation
Note: A one must be written to bit 0 of regis-
ter 01H to set the transmitted DS3 X-bits to
1.
Framed all ones & C-bits set to 1
Unframed 1010 pattern
Unframed all ones pattern
Description
Ed. 4, August 1998
TXC-03303
TXC-03303-MB
M13E

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