FLLXT384BE.A5 Intel, FLLXT384BE.A5 Datasheet - Page 107

• Manufacturer Part Number: FLLXT384BE.A5
• Manufacturer: Intel

Specifications of FLLXT384BE.A5

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 66. Intel
Table 66
Clock recovery capture range
Receive clock duty cycle
Receive clock pulse width
Receive clock pulse width Low time
Receive clock pulse width High time
Rise/fall time
RPOS/RNEG pulse width (MCLK=H)
RPOS/RNEG to RCLK rising setup time
RCLK Rising to RPOS/RNEG hold time
Delay time between RPOS/RNEG and RCLK
1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and
2. Clock recovery is disabled in this mode.
3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit.
4. For all digital outputs.
minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823).
®
LXT384 Transceiver Receive Timing Characteristics
lists receive timing characteristics for the LXT384 Transceiver.
4
Parameter
1
1
2
Intel
E1
T1
E1
T1
E1
T1
E1
T1
E1
T1
E1
T1
E1
T1
®
Tpwdl
Tpwdl
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Tpwh
Tpwh
Rckd
Sym
Tpwl
Tpwl
Tpw
Tpw
Tsur
Thr
Tr
–
–
–
Min.
447
583
203
259
203
259
200
250
200
200
200
200
40
20
–
–
–
±180
Typ
±80
488
648
244
324
244
324
244
324
244
324
244
324
50
–
–
Max
529
713
285
389
285
389
300
400
60
–
–
–
–
–
–
–
5
ppm Relative to nominal
Unit
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
frequency
MCLK = ±100 ppm
@ CL=15 pF
MCLK = H
Test Condition
3
107