FLLXT384BE.A5 Intel, FLLXT384BE.A5 Datasheet - Page 95

• Manufacturer Part Number: FLLXT384BE.A5
• Manufacturer: Intel

Specifications of FLLXT384BE.A5

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

9.4.5
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 54. Instruction Register (IR)
Table 55. JTAG Timing Characteristics
Figure 18. JTAG Timing
Instruction Register (IR)
The IR is a 3 bit shift register that loads the instruction to be performed. The instructions are shifted
LSB first.
Cycle time
J-TMS/J-TDI to J-TCK rising edge time
J-CLK rising to J-TMS/L-TDI hold time
J-TCLK falling to J-TDO valid
SAMPLE / PRELOAD
TMS
TDO
INTEST_ANALOG
TCK
TDI
Instruction
BYPASS
EXTEST
IDCODE
Table 54
Parameter
shows the valid instruction codes and the corresponding instruction description.
Code #
000
010
100
110
111
Connects the BSR to TDI and TDO. Input pins values are loaded into the
BSR. Output pins values are loaded from the BSR.
Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through
AT1 and AT2. Refer to
Connects the BSR to TDI and TDO. The normal path between the LXT384
Transceiver logic and the I/O pins is maintained. The BSR is loaded with the
signals in the I/O pins.
Connects the IDR to the TDO pin.
Serial data from the TDI input is passed to the TDO output through the 1 bit
Bypass Register.
tSUR
Intel
tHT
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Tdod
Sym
Tcyc
Tsut
Tht
Min.
200
Table
50
50
tCYC
-
tDOD
52.
Typ
-
-
-
-
Comments
Max
50
-
-
-
Unit
ns
ns
ns
ns
Test Conditions
95