FLLXT384BE.A5 Intel, FLLXT384BE.A5 Datasheet - Page 117

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FLLXT384BE.A5

Manufacturer Part Number
FLLXT384BE.A5
Description
Manufacturer
Intel
Datasheet

Specifications of FLLXT384BE.A5

Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Figure 26. Motorola Processor Multiplexed Interface - Read Timing
D7-D0
R/W
ACK
INT
AS
CS
DS
Figure 26
multiplexed interface, and a read cycle takes place.
tSAR
is a timing diagram for the Motorola processor in the Host Processor mode with a
tSRW
tASDS
ADDRESS
tHAR
tSCS
tDACKP
tPDS
Intel
tPACK
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
tVDS
tVAS
DATA OUT
tDSAS
tDZ
tINT
tDACK
tHCS
tHRW
117

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