FLLXT384BE.A5 Intel, FLLXT384BE.A5 Datasheet - Page 60

• Manufacturer Part Number: FLLXT384BE.A5
• Manufacturer: Intel

Specifications of FLLXT384BE.A5

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Intel
6.6
60
Figure 7. Jitter Attenuator
®
RPOSi
TNEGi
RNEGi
TPOSi
RCLKi
TCLKi
MCLK
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Jitter Attenuation
Figure 7
an external crystal nor a reference clock that has a frequency higher than the line frequency.
Data signals are clocked into the FIFO with the associated clock signal (TCLKi or RCLKi) and are
clocked out of the FIFO with the JA clock after removing jitter (TCLKo when TCLKi is used, or
RCLKo when RCLKi is used). When the FIFO is within two bits of overflowing or underflowing,
the FIFO adjusts the output clock by
constant throughput delay of either 16 bits (when a 32 x 2-bit register is used) or 32 bits (when a 64
x 2-bit register is used).
JASEL0-1
shows the internal LXT384 Transceiver jitter attenuation (JA) unit, which requires neither
x 32
IN CLK
IN
Clock Recovery Unit
1/8
FIFO
FIFO64
of a bit period. For the associated path, the JA produces a
OUT CLK
OUT
o = outputs
i = inputs
Revision Date: November 28, 2005
JASEL0-1
Document Number: 248994
GCR control bits
Revision Number: 005
TPOSo
RPOSo
TNEGo
RNEGo
TCLKo
RCLKo