FLLXT384BE.A5 Intel, FLLXT384BE.A5 Datasheet - Page 31

• Manufacturer Part Number: FLLXT384BE.A5
• Manufacturer: Intel

Specifications of FLLXT384BE.A5

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 9.
Framer/Mapper Transmit Signals (Sheet 1 of 3)
TCLK7
TCLK6
TCLK5
TCLK4
TCLK3
TCLK2
TCLK1
TCLK0
Signal
Name
QFP
100
107
Pin
74
81
29
36
2
9
PBGA
Ball
D14
B14
N14
L14
D1
N1
B1
L1
Intel
Signal
Type
DI
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Transmit Clock Input 7:0.
When the LXT384 Transceiver is in Hardware mode and
TCLK is:
)
NOTE: When the LXT384 Transceiver is in the Host
When pulse shaping is disabled, it is possible to overheat
and damage the LXT384 Transceiver by leaving transmit
inputs high continuously. For example a programmable
ASIC might leave all outputs high over an extended period,
until it is programmed. To prevent this, clock one of these
signals: TPOS, TNEG, TCLK, or MCLK. Another solution is
to set one of these signals low: TPOS, TNEG, TCLK, or OE.
Note: The TAOS generator uses MCLK as a timing
• Operating with a normal clock signal, TPOS and TNEG
• Low and remains in a low state, the transmitter output
• High (for more than 16 consecutive MCLK clock
are sampled on the falling edge of TCLK.
drivers enter a low-power high-impedance tristate.
cycles), and MCLK is:
• operating normally as a clock, the LXT384
• not operating as a clock, but is either low or high, the
Transceiver enters the TAOS mode. (For details, see
Section 6.8, “Transmit All Ones
pulse-shaper circuit shown in
For information on how to prevent damage to the
LXT384 Transceiver when pulse shaping is disabled,
see
reference. In order to assure that the output
frequency is within specification limits, MCLK must
have the applicable stability.
Normal Clock
Processor mode, TAOS mode can be selected
using registers in
MCLK cycles
MCLK cycles
consecutive
consecutive
High for 16
High for 16
Section 6.4.2, “Transmitter Pulse
TCLK
Low
Signal Description
Normal
high or
MCLK
Either
Don’t
Don’t
Clock
Chapter 8.0,
care
care
low
TNEG and TPOS
sampled on falling
edge of TCLK
Transmitter driver
outputs enter high-
impedance tristate
Disables transmit
pulse shaping
TAOS
Figure 1
Operations”.
“Registers”.
Result
Shaping”.)
is disabled.
31