EELXT360PE.A2-868068 Cortina Systems Inc, EELXT360PE.A2-868068 Datasheet - Page 12

• Manufacturer Part Number: EELXT360PE.A2-868068
• Manufacturer: Cortina Systems Inc

Specifications of EELXT360PE.A2-868068

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT360 Transceiver
Datasheet: Long Form
249231, Revision 2.1
24 January 2008
Table 3
Cortina Systems
19
20
21
22
23
24
25
26
27
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V ≤ Midrange ≤ 2.7 V. Midrange may also be established by letting the pin float.
24
25
27
29
31
32
35
36
37
LXT360 Transceiver Signal Descriptions (Sheet 4 of 5)
®
LXT360 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
LLOOP/SCLK
RLOOP/ CS
EC3/SDO
EC2/SDI
EC1/INT
RRING
RTIP
GND
VCC
DI/O
DI
DI
DI
DI
AI
-
-
Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received
from the line is applied at these pins. A 1:1 transformer is required. Data
and clock recovered from RTIP/RRING are output on the RPOS/RNEG (or
RDATA in Unipolar mode), and RCLK pins.
+5 VDC Power Supply for all circuits except the transmit drivers. Transmit
drivers are supplied by TVCC.
Ground return for power supply VCC.
HARDWARE MODES:
Equalization Control 1-3. EC1, EC2, and EC3 (along with the EC4 pin)
specify the pulse equalization, line build out and equalizer gain limit
settings. See
HOST MODES:
Interrupt. INT goes Low to flag the host when LOS, AIS, NLOOP , QRSS,
DFMS or DFMO bits changes state, or when an elastic store overflow or
underflow occurs. To identify the specific interrupt, read the Performance
Status Register (PSR). T o clear or mask an interrupt, write a one to the
appropriate bit in the Interrupt Clear Register (ICR). T o re-enable the
interrupt, write a zero. INT is an open drain output that must be
connected to VCC through a pull-up resistor.
Serial Data Input. SDI inputs the 16-bit serial address/command and data
word. SDI is sampled on the rising edge of SCLK. Timing is shown in
Figure 18 on page 48
Serial Data Output. SDO outputs the 8-bit serial data read from the
selected LXT360 register. When the CLKE pin is High, SDO is valid on the
rising edge of SCLK. When CLKE is Low, SDO is valid on the falling edge
of SCLK. SDO goes to a high-impedance state when the serial port is being
written to or when CS is High. Timing is shown in
HARDWARE MODES:
Remote Loopback. When held High, the clock and data inputs from the
framer (TPOS/TNEG or TDATA) are ignored and the data received from the
twisted-pair line is transmitted back onto the line at the RCLK frequency.
Connect to Midrange
(NLOOP).
HOST MODES:
Chip Select. CS is used to access the serial interface. For each read or
write operation, CS must transition from High to Low, and remain Low.
HARDWARE MODES:
Local Loopback. When held High, the data on TPOS and TNEG loops
back digitally to the RPOS and RNEG outputs (through the JA if enabled).
Connecting this pin to Midrange
TRING are looped back to RTIP and RRING).
HOST MODES:
Serial Clock. SCLK synchronizes serial port read/write operations. The
clock frequency can be any rate up to 2.048 MHz.
Table 10 on page 31
2
.
to enable In-band Network loopback detection
2
TM
TM
enables Analog loopback (TTIP and
for details.
1.1 Mode Dependent Signals
Figure 19 on page 49
Page 12
.