EELXT360PE.A2-868068 Cortina Systems Inc, EELXT360PE.A2-868068 Datasheet - Page 17

• Manufacturer Part Number: EELXT360PE.A2-868068
• Manufacturer: Cortina Systems Inc

Specifications of EELXT360PE.A2-868068

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT360 Transceiver
Datasheet: Long Form
249231, Revision 2.1
24 January 2008
2.4
2.5
2.6
Cortina Systems
device to operate in Monitor mode. Note that the LXT360 Transceiver must be in T1/E1
long-haul receiver mode (set bits CR1.EC4:1 = 0xx0, 1001, or 1010) to enable Monitor
mode. Note that the Monitor mode feature is not available in Hardware mode.
In Monitor mode, the receive equalizer will handle signals attenuated resistively by 20 to 30
dB, along with 0 to 6 dB of cable attenuation for both E1 and T1 applications.
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides the jitter attenuation
function. The JAL requires no special circuitry, such as an external quartz crystal or high-
frequency clock (higher than the line rate). Rather, its timing reference is MCLK.
In Hardware mode, the ES is a 32 x 2-bit register. Setting the JASEL pin High places the JA
circuitry in the receive data path; setting JASEL Low places the JA in the transmit data path;
setting it to Midrange disables the JA.
In Host mode, bit CR1.JASEL0 enables or disables the JA circuit while bit CR1.JASEL1
controls the JA circuit placement as specified in
32 x 2-bit or 64 x 2-bit register depending on the value of bit CR3.ES64 (see
page
The device clocks data into the ES using either TCLK or RCLK depending on whether the
JA circuitry is in the transmit or receive data path, respectively. Data is shifted out of the
elastic store using the dejittered clock from the JAL. When the FIFO is within two bits of
overflowing or underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES
produces an average delay of 16 bits in the data path. An average delay of 32 bits occurs
when the 64-bit ES option selected (Host mode only). In the event of a LOS condition, with
the Jitter Attenuator in the receive path, RCLK will be derived from MCLK.
Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store
overflow or underflow, respectively. Note that these are “sticky bits”, that is, once set to 1, they
remain set until the host reads the register. An ES overflow or underflow condition will
generate a maskable interrupt.
Hardware Mode
The LXT360 Transceiver operates in Hardware mode when the MODE pin is set to Low or
Midrange. In Hardware mode, individual pins are used to access and control the transceiver.
In Hardware mode, RPOS/RNEG or RDATA are valid on the rising edge of RCLK.
Some functions, such as interrupt (INT), clock edge selection (CLKE), and various
diagnostic modes, are provided only in Host mode.
Host Mode
The LXT360 Transceiver operates in Host mode when the MODE pin is set High. In Host
mode a microprocessor controls the LXT360 Transceiver and reads its status via the serial
port which provides access to the LXT360 Transceiver’s internal registers.
The host microprocessor can completely configure the device, as well as get a full diagnostic/
status report, via the serial port. However, in Unipolar mode, bipolar violation (BPV)
insertions and logic error insertions are controlled by the BPV and INSLER pins, respectively.
Similarly, the recovered clock, data, and BPV detection are available only at output pins. All
other mode settings and diagnostic information are available via the serial port. See
3.0, Register Definitions, on page 30
®
LXT360 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
32).
for details.
Table 9 on page
TM
TM
31. The ES can be either a
2.4 Jitter Attenuation
Table 12 on
Section
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