EELXT360PE.A2-868068 Cortina Systems Inc, EELXT360PE.A2-868068 Datasheet - Page 18

• Manufacturer Part Number: EELXT360PE.A2-868068
• Manufacturer: Cortina Systems Inc

Specifications of EELXT360PE.A2-868068

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT360 Transceiver
Datasheet: Long Form
249231, Revision 2.1
24 January 2008
2.6.1
Table 4
Cortina Systems
Figure 4 on page 19
through a 16-bit word composed of an 8-bit Command/Address byte (bits R/W and A1-A7)
and a subsequent 8-bit data byte (bits D0-7). The R/W bit commands a read or a write
operation, i.e., the direction of the following byte. Bits A1 through A6, of the command/
address byte, point to a specific register. Note that the LXT360 Transceiver address decoder
ignores bits A0 and A7. Refer to
Host mode also allows control of data output timing. The CLKE pin determines when SDO is
valid, relative to the Serial Clock (SCLK) as shown in
Interrupt Handling
In Host mode, the LXT360 Transceiver provides a latched interrupt output pin (INT). When
enabled, a change in any of the Performance Status Register bits will generate an interrupt.
An interrupt can also be generated when the elastic store overflows (TSR.ESOVR) or
underflows (TSR.ESUNF). When an interrupt occurs, the INT output pin is pulled Low. Note
that the output stage of the INT pin has internal pull-down only. Therefore, each device that
shares the INT line requires an external pull-up resistor.
The interrupt is cleared when the interrupt condition no longer exists, and the host processor
writes a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR).
Leaving a 1 in any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.
CLKE Pin Settings
®
1. The clock edge selection feature is not available in Hardware mode.
LXT360 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
CLKE Pin
High
Low
1
shows the serial port data structure. The registers are accessible
Table 35 on page 48
Output
RDATA
RDATA
RPOS
RNEG
RPOS
RNEG
SDO
SDO
Table 4 on page
for timing specifications.
TM
TM
Valid Clock Edge
Falling RCLK
Falling SCLK
Rising RCLK
Rising SCLK
18.
2.6 Host Mode
Page 18