EELXT360PE.A2-868068 Cortina Systems Inc, EELXT360PE.A2-868068 Datasheet - Page 26

• Manufacturer Part Number: EELXT360PE.A2-868068
• Manufacturer: Cortina Systems Inc

Specifications of EELXT360PE.A2-868068

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT360 Transceiver
Datasheet: Long Form
249231, Revision 2.1
24 January 2008
Figure 11
Cortina Systems
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data
stream by causing a Low-to-High transition on the INSLER pin. However, if no logic or bit
errors are to be inserted into the QRSS pattern, INSLER must remain Low. Logic Error
insertion waits until the next bit if the current bit is “jammed”. When there are more than 14
consecutive 0s, the output is jammed to a 1.
A Low-to-High transition on the INSBPV pin will insert a bipolar violation in the QRSS
pattern. Note that the BPV insertion occurs regardless of whether the device is in Bipolar or
Unipolar operating mode.
In Hardware mode, connecting the TAOS pin to Midrange enables QRSS transmission. In
Host mode, setting bits CR2.EPAT0 = 0 and CR2.EPAT1=1 enables QRSS.
QRSS Mode
Selecting QRSS mode also enables QRSS Pattern Detection (QPD) in the receive path. The
QRSS pattern is synchronized when there are fewer than four errors in 128 bits. After
achieving synchronization the device drives the QPD pin Low. In the QRSS mode, any
subsequent bit error in the QRSS pattern causes QPD to go High for half an RCLK clock
cycle. Note that in Host mode, the precise relationship between QPD and RCLK depends on
the CLKE pin. When CLKE is Low, QPD goes High while RCLK is High; when CLKE is High,
QPD goes High while RCLK is Low. The edge of QPD can serve as a trigger for an external
bit-error counter. A LOS condition or a loss of QRSS synchronization will cause QPD to go
High continuously. In this case, and with either Unipolar mode or the encoders/decoders
enabled, the BPV pin indicates BPVs, CODEVs or ZEROVs.
Host mode can generate an interrupt to indicate that QRSS detection has occurred, or that
synchronization is lost. This interrupt is enabled when bit ICR.CQRSS = 0. If the QPD signal
is used to trigger a bit error counter, the interrupt could be used to start or reset the error
counter.
The PSR.QRSS bit provides an indication of QRSS pattern synchronization. This bit goes to
0 when the QRSS pattern is not detected (i.e., when there are more than four errors in 128
bits). The TQRSS bit in the Transition Status Register indicates that QRSS status has
changed since the last QRSS Interrupt Clear command.
®
LXT360 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
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2.7 Diagnostic Mode Operation
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