82V2041EPPG IDT, Integrated Device Technology Inc, 82V2041EPPG Datasheet
82V2041EPPG
Specifications of 82V2041EPPG
Related parts for 82V2041EPPG
82V2041EPPG Summary of contents
Page 1
FEATURES • Single channel T1/E1/J1 short haul line interfaces • Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays • Programmable T1/E1/J1 switchability allowing one bill of ma- terial for any line condition • Single 3.3 V power ...
Page 2
IDT82V2041E FUNCTIONAL BLOCK DIAGRAM LOS/AIS LOS Detector RCLK B8ZS/ RD/RDP HDB3/AMI CV/RDN Decoder PRBS Detector Remote Loopback IBLC Detector TCLK B8ZS/ TD/TDP HDB3/AMI TDN Decoder PRBS Generator IBLC Generator TAOS Clock Software Control Interface Generator Functional Block Diagram SINGLE CHANNEL ...
Page 3
IDT82V2041E Pin Configurations ............................................................................................... 8 2 Pin Description ............................................................................................................................ 9 3 Functional Description .............................................................................................................. 15 3.1 Control Mode Selection .................................................................................................... 15 3.2 T1/E1/J1 Mode Selection .................................................................................................. 15 3.3 Transmit Path ................................................................................................................... 15 3.3.1 Transmit Path System Interface.............................................................................. 15 3.3.2 ...
Page 4
IDT82V2041E 3.8.4 Inband Loopback .................................................................................................... 30 3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 30 3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 30 3.8.4.3 Automatic Remote Loopback .................................................................. 31 3.9 Error Detection/Counting And Insertion ............................................................................ 32 3.9.1 Definition Of Line Coding Error ............................................................................... 32 3.9.2 ...
Page 5
Table-1 Pin Description ................................................................................................................ 9 Table-2 Transmit Waveform Value For E1 75 ohm.................................................................... 17 Table-3 Transmit Waveform Value For E1 120 ohm.................................................................. 18 Table-4 Transmit Waveform Value For T1 0~133 ft................................................................... 18 Table-5 Transmit Waveform Value For T1 133~266 ft............................................................... ...
Page 6
IDT82V2041E Table-42 INTES: Interrupt Trigger Edge Select Register ............................................................. 49 Table-43 STAT0: Line Status Register 0 (real time status monitor)............................................. 50 Table-44 STAT1: Line Status Register 1 (real time status monitor)............................................. 51 Table-45 INTS0: Interrupt Status Register 0 ................................................................................ 52 ...
Page 7
Figure-1 Block Diagram ................................................................................................................. 2 Figure-2 IDT82V2041E TQFP44 Package Pin Assignment .......................................................... 8 Figure-3 E1 Waveform Template Diagram .................................................................................. 16 Figure-4 E1 Pulse Template Test Circuit ..................................................................................... 16 Figure-5 DSX-1 Waveform Template .......................................................................................... 16 Figure-6 T1 Pulse Template Test Circuit ...
Page 8
IDT82V2041E 1 IDT82V2041E PIN CONFIGURATIONS IC VDDT TRING TTIP GNDT GNDA RRING RTIP VDDA REF IC Figure-2 IDT82V2041E TQFP44 Package Pin Assignment IDT82V2041E Pin Configurations SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT IDT82V2041E 39 ...
Page 9
IDT82V2041E 2 PIN DESCRIPTION Table-1 Pin Description Name Type Pin No. TTIP Analog 37 TTIP/TRING: Transmit Bipolar Tip/Ring TRING output 36 These pins are the differential line driver outputs. They will be in high impedance state under the following conditions: ...
Page 10
IDT82V2041E Table-1 Pin Description (Continued) Name Type Pin No. RCLK O 4 RCLK: Receive Clock output This pin outputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS condition with AIS enabled (bit AISE=1), ...
Page 11
IDT82V2041E Table-1 Pin Description (Continued) Name Type Pin No CS: Chip Select In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial or parallel microcontroller ...
Page 12
IDT82V2041E Table-1 Pin Description (Continued) Name Type Pin No. SDO O 23 SDO: Serial Data Output In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at SDO pin is clocked ...
Page 13
IDT82V2041E Table-1 Pin Description (Continued) Name Type Pin No. AD6 I/O 32 AD6: Address/Data Bus bit6 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin ...
Page 14
IDT82V2041E Table-1 Pin Description (Continued) Name Type Pin No. JA1 I 15 JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select (only used for hardware control mode) • • • • In software control mode, this pin should ...
Page 15
IDT82V2041E 3 FUNCTIONAL DESCRIPTION 3.1 CONTROL MODE SELECTION The IDT82V2041E can be configured by software or by hardware. The software control mode supports Serial Control Interface, Motorola Multi- plexed Control Interface and Intel Multiplexed Control Interface. The Con- trol mode ...
Page 16
IDT82V2041E ...
Page 17
IDT82V2041E 3.3.3.2 USER-PROGRAMMABLE ARBITRARY WAVEFORM When the PULS[3:0] bits are set to ‘11xx’, user-programmable arbitrary waveform generator mode can be used. This allows the transmitter perfor- mance to be tuned for a wide variety of line condition or special application. ...
Page 18
IDT82V2041E Table-3 Transmit Waveform Value For E1 120 ohm Sample 0000000 0000000 2 0000000 0000000 3 0000000 0000000 4 0001111 0000000 5 0111100 0000000 6 0111100 0000000 7 0111100 0000000 8 0111100 0000000 9 0111100 ...
Page 19
IDT82V2041E Table-7 Transmit Waveform Value For T1 399~533 ft Sample 0100000 1000011 2 0111011 1000010 3 0110101 1000001 4 0101111 0000000 5 0101110 0000000 6 0101101 0000000 7 0101100 0000000 8 0101010 0000000 9 0101000 ...
Page 20
IDT82V2041E 3.3.4 TRANSMIT PATH LINE INTERFACE The transmit line interface consists of TTIP pin and TRING pin. The impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. If T_TERM[2] is set to ...
Page 21
IDT82V2041E 3.4 RECEIVE PATH The receive path consists of Receive Internal Termination, Monitor Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive Equalizer, Data Slicer, CDR (Clock & Data Recovery), Optional Jitter Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-7. 3.4.1 ...
Page 22
IDT82V2041E A R Line Line X Note: 1. Common decoupling capacitor, one per chip 2. Cp 0-560 (pF D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060 refer ...
Page 23
IDT82V2041E 3.4.3 ADAPTIVE EQUALIZER The Adaptive Equalizer can be enabled to increase the receive sensi- tivity and to allow programming of the LOS level up to -24 dB. See3.6 Los And AIS Detection. It can be enabled or disabled by ...
Page 24
IDT82V2041E 3.4.8 RECEIVE PATH SYSTEM INTERFACE The receive path system interface consists of RCLK pin, RD/RDP pin and RDN pin mode, the RCLK outputs a recovered 2.048 MHz clock. In T1/J1 mode, the RCLK outputs a recovered 1.544 ...
Page 25
IDT82V2041E Table-12 Criteria of Starting Speed Adjustment FIFO Depth Criteria for Adjusting Data Outgoing Speed 32 Bits 2 bits close to its full or emptiness 64 Bits 3 bits close to its full or emptiness 128 Bits 4 bits close ...
Page 26
IDT82V2041E Table-13 LOS Declare and Clear Control bit T1E1 LAC Level < 800 mVpp 0=T1.231 N=175 bits 1=T1/J1 Level < 800 mVpp 1=I.431 N=1544 bits Level < 800 mVpp 0=G.775 N=32 bits 0=E1 Level < 800 mVpp 1=I.431/ETSI N=2048 bits ...
Page 27
IDT82V2041E (MAINT0, 0DH). Table-15 summarizes different criteria for AIS detection Declaring/Clearing. Table-15 AIS Condition ITU G.775 for E1 (LAC bit is set to ‘0’ by default) AIS Less than 3 zeros contained in each of two consecutive 512-bit streams are ...
Page 28
IDT82V2041E 3.7 TRANSMIT AND DETECT INTERNAL PATTERNS The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and Activate/Deactivate Loopback Code) will be generated and detected by IDT82V2041E. TCLK is used as the reference clock by default. MCLK can also be ...
Page 29
IDT82V2041E LOS/AIS LOS Detection RCLK B8ZS/ RD/RDP HDB3/AMI CV/RDN Decoder B8ZS/ TCLK HDB3/AMI TD/TDP Encoder TDN LOS/AIS LOS Detection RCLK B8ZS/ HDB3/AMI RD/RDP Attenuator CV/RDN Decoder B8ZS/ TCLK HDB3/AMI TD/TDP Attenuator Encoder TDN Functional Description SINGLE CHANNEL T1/E1/J1 SHORT HAUL ...
Page 30
IDT82V2041E LOS/AIS LOS Detection RCLK B8ZS/ RD/RDP HDB3/AMI CV/RDN Decoder Remote Loopback B8ZS/ TCLK HDB3/AMI TD/TDP Encoder TDN 3.8.4 INBAND LOOPBACK When PATT[1:0] bits (MAINT0, 0DH) are set to ‘11’, the IDT82V2041E is configured in Inband Loopback mode. In this ...
Page 31
IDT82V2041E 3.8.4.3 AUTOMATIC REMOTE LOOPBACK When ARLP bit (MAINT1, 0EH) is set to ‘1’, the IDT82V2041E is con- figured into the Automatic Remote Loopback mode. In this mode, if the Acti- vate Loopback Code has been detected in the receive ...
Page 32
IDT82V2041E 3.9 ERROR DETECTION/COUNTING AND INSERTION 3.9.1 DEFINITION OF LINE CODING ERROR The following line encoding errors can be detected and counted by the IDT82V2041E: • Received Bipolar Violation (BPV) Error: In AMI coding, when two consecutive pulses of the ...
Page 33
IDT82V2041E • Manual Report Mode In Manual Report Mode, the internal Error Counter starts to count the received errors when the CNT_MD bit (MAINT6, 13H) is set to ‘0’. When there is a ‘0’ to ‘1’ transition on the CNT_TRF ...
Page 34
IDT82V2041E 3.11 MCLK AND TCLK 3.11.1 MASTER CLOCK (MCLK) MCLK is an independent, free-running reference clock. MCLK is 1.544 MHz for T1/J1 applications and 2.048 MHz in E1 mode. This reference clock is used to generate several internal reference signals: ...
Page 35
IDT82V2041E 3.12 MICROCONTROLLER INTERFACES The microcontroller interface provides access to read and write the reg- isters in the device. The chip supports serial microcontroller interface and two kinds of parallel microcontroller interface: Motorola multiplexed mode and Intel multiplexed mode. Different ...
Page 36
IDT82V2041E Table-18 Interrupt Event Interrupt Event LOS Detected AIS Detected Driver Failure Detected TCLK Loss Synchronization Status of PRBS/QRSS PRBS/QRSS Error Code Violation Received Excessive Zeros Received JA FIFO Overflow JA FIFO Underflow Inband Loopback Activate Code Status Inband Loopback ...
Page 37
IDT82V2041E 4 PROGRAMMING INFORMATION 4.1 REGISTER LIST AND MAP The registers banks include control registers, status registers and counter registers. Table-19 Register List and Map Address (hex) Register R/W Control Registers RST W 02 GCF R/W ...
Page 38
IDT82V2041E 4.3 REGISTER DESCRIPTION 4.3.1 CONTROL REGISTERS Table-20 ID: Device Revision Register (R, Address = 00H) Symbol Bit Default ID[7:0] 7-0 00H Table-21 RST: Reset Register (W, Address = 01H) Symbol Bit Default RST[7:0] 7-0 00H Table-22 GCF: Global Configuration ...
Page 39
IDT82V2041E Table-24 JACF: Jitter Attenuation Configuration Register (R/W, Address = 04H) Symbol Bit Default - 7-6 00 JA_LIMIT 5 1 JACF[1:0] 4-3 00 JADP[1:0] 2-1 00 JABW 0 0 Programming Information SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Reserved. ...
Page 40
IDT82V2041E 4.3.2 TRANSMIT PATH CONTROL REGISTERS Table-25 TCF0: Transmitter Configuration Register 0 (R/W, Address = 05H) Symbol Bit Default - 7-5 000 T_OFF 4 0 TD_INV 3 0 TCLK_SEL 2 0 T_MD[1:0] 0-1 00 Table-26 TCF1: Transmitter Configuration Register 1 ...
Page 41
IDT82V2041E Table-27 TCF2: Transmitter Configuration Register 2 (R/W, Address = 07H) Symbol Bit Default - 7-6 00 SCAL[5:0] 5-0 100001 Table-28 TCF3: Transmitter Configuration Register 3 (R/W, Address = 08H) Symbol Bit Default DONE UI[1:0] ...
Page 42
IDT82V2041E 4.3.3 RECEIVE PATH CONTROL REGISTERS Table-30 RCF0: Receiver Configuration Register 0 (R/W, Address = 0AH) Symbol Bit Default - 7-5 000 R_OFF 4 0 RD_INV 3 0 RCLK_SEL 2 0 R_MD[1:0] 1-0 00 Table-31 RCF1: Receiver Configuration Register 1 ...
Page 43
IDT82V2041E Table-32 RCF2: Receiver Configuration Register 2 (R/W, Address = 0CH) Symbol Bit Default - 7-6 00 SLICE[1:0] 5 3-2 10 MG[1:0] 1-0 00 Programming Information SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Reserved. Receive slicer threshold ...
Page 44
IDT82V2041E 4.3.4 NETWORK DIAGNOSTICS CONTROL REGISTERS Table-33 MAINT0: Maintenance Function Control Register 0 (R/W, Address = 0DH) Symbol Bit Default - 7 00 PATT[1:0] 6-5 00 PATT_CLK 4 0 PRBS_INV 3 0 LAC 2 0 AISE 1 0 ATAO 0 ...
Page 45
IDT82V2041E Table-35 MAINT2: Maintenance Function Control Register 2 (R/W, Address = 0FH) Symbol Bit Default - 7-6 00 TIBLB_L[1:0] 5-4 00 RIBLBA_L[1:0] 3-2 00 RIBLBD_L[1:0] 1-0 01 Table-36 MAINT3: Maintenance Function Control Register 3 (R/W, Address = 10H) Symbol Bit ...
Page 46
IDT82V2041E Table-39 MAINT6: Maintenance Function Control Register 6 (R/W, Address = 13H) Symbol Bit Default - 7 0 BPV_INS 6 0 ERR_INS 5 0 EXZ_DEF 5 0 ERR_SEL 3-2 00 CNT_MD 1 0 CNT_TRF 0 0 Programming Information SINGLE CHANNEL ...
Page 47
IDT82V2041E 4.3.5 INTERRUPT CONTROL REGISTERS Table-40 INTM0: Interrupt Mask Register 0 (R/W, Address = 14H) Symbol Bit Default - 7 1 IBLBA_IM 6 1 IBLBD_IM 5 1 PRBS_IM 4 1 TCLK_IM 3 1 DF_IM 2 1 AIS_IM 1 1 LOS_IM ...
Page 48
IDT82V2041E Table-41 INTM1: Interrupt Masked Register 1 (R/W, Address = 15H) Symbol Bit Default DAC_OV_IM 7 1 JAOV_IM 6 1 JAUD_IM 5 1 ERR_IM 4 1 EXZ_IM 3 1 CV_IM 2 1 TIMER_IM 1 1 CNT_IM 0 1 Programming Information ...
Page 49
IDT82V2041E Table-42 INTES: Interrupt Trigger Edge Select Register (R/W, Address = 16H) Symbol Bit Default - 7 0 IBLBA_IES 6 0 IBLBD_IES 5 0 PRBS_IES 4 0 TCLK_IES 3 0 DF_IES 2 0 AIS_IES 1 0 LOS_IES 0 0 Programming ...
Page 50
IDT82V2041E 4.3.6 LINE STATUS REGISTERS Table-43 STAT0: Line Status Register 0 (real time status monitor) (R, Address = 17H) Symbol Bit Default - 7 0 IBLBA_S 6 0 IBLBD_S 5 0 PRBS_S 4 0 TCLK_LOS 3 0 Programming Information SINGLE ...
Page 51
IDT82V2041E Table-43 STAT0: Line Status Register 0 (real time status monitor) (Continued) (R, Address = 17H) Symbol Bit Default DF_S 2 0 AIS_S 1 0 LOS_S 0 0 Table-44 STAT1: Line Status Register 1 (real time status monitor) (R, Address ...
Page 52
IDT82V2041E 4.3.7 INTERRUPT STATUS REGISTERS Table-45 INTS0: Interrupt Status Register 0 (R, Address = 19H) (this register is reset and relevant interrupt request is cleared after a read) Symbol Bit Default - 7 0 IBLBA_IS 6 0 IBLBD_IS 5 0 ...
Page 53
IDT82V2041E Table-46 INTS1: Interrupt Status Register 1 (R, Address = 1AH) (this register is reset and the relevant interrupt request is cleared after a read) Symbol Bit Default DAC_OV_IS 7 0 JAOV_IS 6 0 JAUD_IS 5 0 ERR_IS 4 0 ...
Page 54
IDT82V2041E 4.3.8 COUNTER REGISTERS Table-47 CNT0: Error Counter L-byte Register 0 (R, Address = 1BH) Symbol Bit Default CNT_L[7:0] 7-0 00H Table-48 CNT1: Error Counter H-byte Register 1 (R, Address = 1CH) Symbol Bit Default CNT_H[7:0] 7-0 00H Programming Information ...
Page 55
IDT82V2041E 5 HARDWARE CONTROL PIN SUMMARY Table-49 Hardware Control Pin Summary Pin No. Symbol TQFP 17 MODE1 MODE[1:0]: Operation mode of control interface select 16 MODE0 00= Hardware interface 01= Serial interface 10= Parallel – multiplexed – Motorola Interface 11= ...
Page 56
IDT82V2041E Table-49 Hardware Control Pin Summary (Continued) Pin No. Symbol TQFP 22 MONT MONT: Receive monitor n gain select LP1 LP[1:0]: Loopback mode select 24 LP0 00= no loopback 01= analog ...
Page 57
IDT82V2041E 6 TEST SPECIFICATIONS Table-50 Absolute Maximum Rating Symbol VDDA, VDDD Core Power Supply VDDIO I/O Power Supply VDDT Transmit Power Supply Input Voltage, Any Digital Pin Vin Input Voltage, Any RTIP and RRING pin ESD Voltage, any pin Transient ...
Page 58
IDT82V2041E Table-52 Power Consumption Symbol E1, 3 Ω Load E1, 3.3 V, 120 Ω Load 3 T1, 3.3 V, 100 Ω Load J1, 3.3 V, 110 Ω Load 1.Maximum power and current consumption over the full operating temperature ...
Page 59
IDT82V2041E Table-54 E1 Receiver Electrical Characteristics Symbol Parameter Receiver sensitivity Adaptive Equalizer Disabled: Adaptive Equalizer Enabled: Analog LOS level Adaptive Equalizer Disabled: Adaptive Equalizer Enabled: Allowable consecutive zeros before LOS G.775: I.431/ETSI300233: LOS reset Receive Intrinsic Jitter ...
Page 60
IDT82V2041E Table-55 T1/J1 Receiver Electrical Characteristics Symbol Parameter sensitivity Analog LOS level Allowable consecutive zeros before LOS T1.231-1993 I.431 LOS reset Receive Intrinsic Jitter kHz kHz 8 kHz - 40 kHz Wide ...
Page 61
IDT82V2041E Table-56 E1 Transmitter Electrical Characteristics Symbol Vo-p Output pulse amplitudes E1, 75 Ω load E1, 120 Ω load Vo-s Zero (space) level E1, 75 Ω load E1, 120 Ω load Transmit amplitude variation with supply Difference between pulse sequences ...
Page 62
IDT82V2041E Table-57 T1/J1 Transmitter Electrical Characteristics Symbol Vo-p Output pulse amplitudes Vo-s Zero (space) level Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses (T1.102) TPW Output Pulse Width at 50% of nominal amplitude Pulse width ...
Page 63
IDT82V2041E Table-58 Transmitter and Receiver Timing Characteristics Symbol MCLK frequency E1: T1/J1: MCLK tolerance MCLK duty cycle Transmit path TCLK frequency E1: T1/J1: TCLK tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data Hold Time Delay time ...
Page 64
IDT82V2041E TCLK TD/TDP TDN RCLK RDP/RD (RCLK_SEL = 0 software mode) (RCLKE = 0 hardware mode) RDN/CV RDP/RD (RCLK_SEL = 1 software mode) (RCLKE = 1 hardware mode) RDN/CV Table-59 Jitter Tolerance Jitter Tolerance E1 – ...
Page 65
IDT82V2041E Test Specifications SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Figure-22 E1 Jitter Tolerance Performance 65 December 9, 2005 ...
Page 66
IDT82V2041E Test Specifications SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Figure-23 T1/J1 Jitter Tolerance Performance 66 December 9, 2005 ...
Page 67
IDT82V2041E Table-60 Jitter Attenuator Characteristics Parameter Jitter Transfer Function Corner (-3 dB) Frequency Jitter Attenuator E1: (G.736 400 Hz @ 100 kHz T1/J1: (Per AT&T pub.62411 ...
Page 68
IDT82V2041E Test Specifications SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Figure-24 E1 Jitter Transfer Performance 68 December 9, 2005 ...
Page 69
IDT82V2041E Test Specifications SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Figure-25 T1/J1 Jitter Transfer Performance 69 December 9, 2005 ...
Page 70
IDT82V2041E 7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS 7.1 SERIAL INTERFACE TIMING Table-61 Serial Interface Timing Characteristics Symbol t1 SCLK High Time t2 SCLK Low Time t3 Active CS to SCLK Setup Time t4 Last SCLK Hold Time to Inactive CS Time ...
Page 71
IDT82V2041E 7.2 PARALLEL INTERFACE TIMING Table-62 Multiplexed Motorola Read Timing Characteristics Symbol tRC Read Cycle Time tDW Valid DS Width tRWV Delay from DS to Valid Read tRWH R Hold Time tASW Valid AS Width tADD Delay from ...
Page 72
IDT82V2041E Table-63 Multiplexed Motorola Write Timing Characteristics Symbol tWC Write Cycle Time tDW Valid DS Width tRWV Delay from DS to Valid Write tRWH R Hold Time tASW Valid AS Width tADD Delay from AS active to DS ...
Page 73
IDT82V2041E Table-64 Multiplexed Intel Read Timing Characteristics Symbol tRC Read Cycle Time tRDW Valid RD Width tARD Delay from ALE to Valid Read tALEW Valid ALE Width tADS Address to ALE Setup Time tADH Address to ALE Hold Time tPRD ...
Page 74
IDT82V2041E Table-65 Multiplexed Intel Write Timing Characteristics Symbol tWC Write Cycle Time tWRW Valid WR Width tALEW Valid ALE Width tAWD Delay from ALE to Valid Write tADS Address to ALE Setup Time tADH Address to ALE Hold Time tDV ...
Page 75
IDT82V2041E IDT82P2816 ORDERING INFORMATION XXXXXXX IDT Device Type DATASHEET DOCUMENT HISTORY 12/09/2005 pgs. 1, 14, 21, 22, 28, 36, 37, 44, 62, 63, 75 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 SINGLE CHANNEL T1/E1/J1 SHORT HAUL ...