82V2041EPPG IDT, Integrated Device Technology Inc, 82V2041EPPG Datasheet - Page 22

• Manufacturer Part Number: 82V2041EPPG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2041EPPG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

select impedance matching for both receiver and transmitter. If TERM pin
is low, external impedance network will be used for impedance matching.
If TERM pin is high, internal impedance will be used for impedance match-
ing and PULS[3:0] pins can be set to select the specific internal impedance.
Refer to
3.4.2
ing on channels located in other chips can be performed by tapping the mon-
itored channel through a high impedance bridging circuit. Refer to
9
RRING is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selected by MG[1:0] bits (RCF2, 0CH). For normal operation, the Monitor
Gain should be set to 0 dB.
Gain. When MONT pin is low, the Monitor Gain is 0 dB. When MONT pin
is high, the Monitor Gain is 26 dB. Refer to
for details.
Monitor Mode
Functional Description
IDT82V2041E
and Figure-11.
In hardware control mode, TERM and PULS[3:0] pins can be used to
In both T1/J1 and E1 short haul applications, the non-intrusive monitor-
After a high resistance bridging circuit, the signal arriving at the RTIP/
In hardware control mode, MONT pin can be used to set the Monitor
Note that LOS indication is not supported if the device is operated in Line
LINE MONITOR
5 Hardware Control Pin Summary
Note: 1. Common decoupling capacitor, one per chip
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060
4. R
T
/ R
R
R
: refer to Table-10 and Table-11 respecivley for R
X
T
Line
X
Line
A
B
5 Hardware Control Pin Summary
•
•
2:1
1:1
for details.
•
•
Cp
Figure-8 Transmit/Receive Line Circuit
R
R
4
•
•
R
R
T
T
VDDA
4
D6
D5
4
•
·
VDDT
VDDA
VDDT
Figure-
D2
D1
D8
D7
D4
D3
•
•
•
·
·
·
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
T
RTIP
RRING
TTIP
TRING
and R
22
R
Figure-9 Monitoring Receive Line in Another Chip
Figure-10 Monitor Transmit Line in Another Chip
values
DSX cross connect
DSX cross connect
point
point
R
R
GNDA
VDDA
GNDT
VDDT
0.1µF
0.1µF
•
•
68µF
68µF
RTIP
TTIP
TRING
RRING
3.3 V
3.3 V
1
1
RRING
RRING
RTIP
RTIP
December 9, 2005
=22/26/32dB
monitor gain
monitor gain
monitor mode
normal transmit mode
normal receive mode
gain=0dB
=22/26/32dB
monitor
monitor gain
monitor mode