FWLXT9785BC Cortina Systems Inc, FWLXT9785BC Datasheet - Page 110

• Manufacturer Part Number: FWLXT9785BC
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785BC

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 39
Cortina Systems
BGA15 Signal Descriptions (Sheet 5 of 7)
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode).
3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode).
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
AMDIX_EN
LINKHOLD
FIFOSEL1
FIFOSEL0
LED0_1_L
LED0_2_L
LED0_3_L
Symbol
CFG_1
CFG_2
CFG_3
Designation
BGA15 Ball
M10,
C1,
L9,
M9
M8
K8
B3
N9
P9
F1
I, ID, ST
I, ID, ST
OD, TS,
I, ST, IP
I, ST, ID
SL, IP
Type
LED Signal Descriptions
Signal Description
Auto MDI/MDIX Enable Default.
This pin is read at startup or reset. Its value at that time is
used to set the default state of Register bit 27.9 for all ports.
These register bits can be read and overwritten after
startup / reset. Refer to
When active (High), automatic MDI crossover (MDIX)
(regardless of segmentation) is selected for all ports. When
inactive (Low) MDIX is selected according to the MDIX pin.
Global Port Configuration Defaults 1-3.
These pins are read at startup or reset. Their value at that
time is used to set the default state of register bits shown in
Table 42, Global Hardware Configuration Settings, on
page 126
overwritten after startup / reset.
When operating in Hardware Control Mode, these pins
provide configuration control options for all the ports (refer
to
FIFO Select <1:0>.
These pins are read at startup or reset. Their value at that
time is used to set the default state of Register bits
18.15:14 for all ports. These register bits can be read and
overwritten after startup/reset.
These pins are shared with RMII-RxER<5:4>. An external
pull-up resistor (see applications section for value) can be
used to set FIFO Select<1:0> to active while RxER<5:4>
are three-stated during hardware reset. If no pull-up is
used, the default FIFO select state is set via the internal
pull-down resistors.
See
page
LINKHOLD Default. This pin is read at startup or reset. Its
value at that time is used to set the default state of Register
bit 0.11 for all ports. This register bit can be read and
overwritten after startup / reset. When High, the LXT9785/
LXT9785E powers down all ports.
This pin is shared with RMII-RxER6. An external pull-up
resistor (see applications section for value) can be used to
set LINKHOLD active while RxER6 is three-stated during
H/W reset. If no pull-up is used, the default LINKHOLD
state is set inactive via the internal pull-down resistor.
Port 0 LED Drivers 1-3.
These pins drive LED indicators for Port 0. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 97, LED Configuration Register (Address 20, Hex
14), on page 204
page 126
Table 36, Receive FIFO Depth Configurations, on
96.
for all ports. These register bits can be read and
for details).
for details).
Table 40 on page
3.6 BGA15 Signal Descriptions
116.
Page 110