FWLXT9785BC Cortina Systems Inc, FWLXT9785BC Datasheet - Page 121

• Manufacturer Part Number: FWLXT9785BC
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785BC

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Figure 12
4.3.10
4.3.11
Cortina Systems
Interrupt Logic
Global Hardware Control Interface
The LXT9785/LXT9785E provides a Hardware Control Interface for applications where
the MDIO is not desired. Refer to
details.
FIFO Initial Fill Values
The FIFO initial fill value sets the number of bits required to be written into the FIFO before
the process of reading the packet out of the FIFO is started. The read operation is aligned
on nibble boundaries because the FIFO is one nibble wide. The read clock on the RMII
and SMII interfaces may occur any time within the next available nibble. Therefore, the
effective size of the FIFO is one nibble less than the selected size.
Large initial fill FIFO settings alter both the data-path latency and the InterFrame Gap
(IFG) output on the RMII and SMII interfaces. The latency values are increased or
decreased depending on the number of bits the FIFO size is increased or decreased. The
IFG may decrease up to twice the size of the initial fill FIFO setting. When the following
three conditions are met, the IPG on the RMII and SMII interfaces may become
nonexistent between packets, effectively concatenating the packets into one long
corrupted packet:
The concatenation of the packets is flagged by the MAC as a CRC error and possibly an
oversized packet depending upon the length indication capabilities of the MAC. The
possibility of packet concatenation can be minimized on the RMII interface by setting the
initial fill FIFO Register bits 18.15:14 to 01. The FIFO setting bits should be set to 10 for
the SMII interfaces.
®
• Duplex status change.
• Link status change.
• Isolate status change.
• The frequency difference between the link partner and the local LXT9785/LXT9785E
• Jumbo packets (8192 byte packets or longer) are used.
• Packets on the wire occur with minimum Inter-Packet Gap (IPG) of 96 bit times.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Interrupt (Event) Status Register is cleared on read.
X = Any Interrupt capability
Force Interrupt
Event X Enable Reg
Event X Status Reg
device exceed 200 ppm (the IEEE standard requirement).
Per Event
. .
.
AND
Interrupt Enable
OR
Section 4.5, Initialization, on page 123
AND
Per port
. . .
Interface (MII) Interfaces
4.3 Media Independent
Port
Combine
Logic
for additional
Interrupt Pin
Page 121