FWLXT9785BC Cortina Systems Inc, FWLXT9785BC Datasheet - Page 84

• Manufacturer Part Number: FWLXT9785BC
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785BC

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 27
Cortina Systems
SS-SMII Specific Signal Descriptions – BGA23
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
3. RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down
BGA23
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
C12,
B15,
B17,
C16
B12
D17
F14
C8,
B11
C7,
A6,
E4,
E3,
B1,
B4,
B9,
Designation
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
modes and during H/W reset.
Ball/Pin
PQFP
204
201
205
197
35
58
17
32
60
21
54
45
36
27
15
7
RxSYNC0
RxSYNC1
TxSYNC0
TxSYNC1
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
Symbol
TxCLK0
TxCLK1
RxCLK0
RxCLK1
O, TS,
O, TS,
O, TS,
Type
I, ID
I, ID
ID
ID
ID
1
Signal Description
SS-SMII Transmit Synchronization.
The MAC must generate a TxSYNC pulse every 10 TxCLK
cycles to mark the start of TxData segments. TxSYNC0 is
used when 1x8 port sectionalization is selected.
SS-SMII Receive Synchronization.
The LXT9785/LXT9785E generates these pulses every 10
RxCLK cycles to mark the start of RxData segments for
the MAC. RxSYNC1 is used when 1x8 port
sectionalization is selected. RxSYNC0 may not be used.
These outputs are only enabled when SS-SMII mode is
enabled.
SS-SMII Transmit Clock.
The MAC sources this 125 MHz clock as the timing
reference for TxData and TxSYNC. Only TxCLK0 is used
when 1x8 port sectionalization is selected.
SS-SMII Receive Clock.
The LXT9785/LXT9785E generates these clocks, based
on REFCLK, to provide a timing reference for RxData and
RxSYNC to the MAC. RxCLK1 is used when 1x8 port
sectionalization is selected. RxCLK0 may not be used.
Receive Data - Ports 0-7.
These serial output streams provide data received from
the network. The LXT9785/LXT9785E drives the data out
synchronously to REFCLK.
2,3
3.4 BGA23 Signal Descriptions
Page 84