FWLXT9785BC Cortina Systems Inc, FWLXT9785BC Datasheet - Page 82

• Manufacturer Part Number: FWLXT9785BC
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785BC

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 24
Cortina Systems
RMII Signal Descriptions – BGA23 (Sheet 3 of 3)
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
BGA23
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
E16,
B12,
D12,
B16,
A12,
A15,
A17,
F14
E15
D17
C4,
D2,
D5,
D7,
C8,
E4,
A5,
B8,
Designation
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
Power-Down modes and during H/W reset.
Ball/Pin
PQFP
198
197
200
201
58
49
39
31
17
10
59
50
40
32
20
11
1
2
RxData7_0
RxData7_1
CRS_DV0
CRS_DV1
CRS_DV2
CRS_DV3
CRS_DV4
CRS_DV5
CRS_DV6
CRS_DV7
Symbol
RxER0
RxER1
RxER2
RxER3
RxER4
RxER5
RxER6
RxER7
O, TS, SL,
O, TS, SL,
O, TS, ID
ID, I, ST
Type
O, TS
ID
1
Signal Description
Receive Data - Port 7.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Carrier Sense/Receive Data Valid - Ports 0-7.
On detection of valid carrier, these signals are
asserted asynchronously with respect to REFCLK.
CRS_DVn is de-asserted on loss of carrier,
synchronous to REFCLK.
Receive Error - Ports 0-7.
These signals are synchronous to the respective
REFCLK. Active High indicates that received code
group is invalid, or that PLL is not locked.
The RxER signals have the following additional
function pins:
RxER0 (MDIX)
RxER1 (PAUSE)
RxER2 (PREASEL)
RxER4 (FIFOSEL0)
RxER5 (FIFOSEL1)
RxER6 {LINKHOLD)
3.4 BGA23 Signal Descriptions
2,3
Page 82