PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 143

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

11.0
FIGURE 11-1:
© 2011-2012 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
Legend:
Note:
2: Some registers and associated bits
I/O PORTS
PIO Module
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120)
Reference Manual”, which is available
from
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
R = Peripheral input buffer types may vary. Refer to
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
WR PORT
RD PORT
Peripheral Input
RD ODC
WR ODC
WR TRIS
Data Bus
RD TRIS
SYSCLK
SYSCLK
WR LAT
RD LAT
Sleep
the
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
in
Microchip
Peripheral Input Buffer
the
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Peripheral Module
“PIC32
web
D
D
D
CK
CK
CK
Family
EN Q
EN Q
EN Q
R
site
Preliminary
Q
Q
Q
in
Table 1-1
ODC
TRIS
LAT
0
1
for peripheral details.
Q
Output Multiplexers
Q
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up and pull-down
• Monitor selective inputs and generate interrupt
• Operation during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
Figure 11-1
multiplexed I/O port.
Synchronization
CK
when change in pin state is detected
registers
D
1
0
1
0
Q
Q
PIC32MX1XX/2XX
illustrates a block diagram of a typical
CK
D
0
1
®
MCU to monitor and control
I/O Cell
DS61168D-page 143
I/O Pin