PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 166

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 16-1:
DS61168D-page 166
Legend:
R = Readable bit
-n = Value at POR
bit 31
bit 30
bit 29
bit 28
bit 27
bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
bit 23
bit 22-18 Unimplemented: Read as ‘0’
bit 17
Note 1:
Range
31:24
23:16
15:8
7:0
Bit
2:
3:
MCLKSEL
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in
0 = Slave select SPI support is disabled.
FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
pulse. This bit is only valid in FRAMED_SYNC mode.
111 = Reserved; do not use
110 = Reserved; do not use
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
MCLKSEL: Master Clock Enable bit
1 = REFCLK is used by the Baud Rate Generator
0 = PBCLK is used by the Baud Rate Generator
SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit can only be written when the ON bit = 0.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
31/23/15/7
FRMEN
SSEN
ON
Master mode. Polarity is determined by the FRMPOL bit.
R/W-0
R/W-0
R/W-0
R/W-0
Bit
(1)
(2)
SPIxCON: SPI CONTROL REGISTER
FRMSYNC
30/22/14/6
R/W-0
R/W-0
CKP
Bit
U-0
U-0
—
—
W = Writable bit
‘1’ = Bit is set
29/21/13/5
FRMPOL
MSTEN
R/W-0
R/W-0
SIDL
R/W-0
Bit
U-0
—
(2)
Preliminary
28/20/12/4
DISSDO
MSSEN
DISSDI
R/W-0
R/W-0
R/W-0
Bit
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FRMSYPW
27/19/11/3
MODE32
R/W-0
R/W-0
R/W-0
Bit
U-0
—
STXISEL<1:0>
26/18/10/2
MODE16
© 2011-2012 Microchip Technology Inc.
R/W-0
R/W-0
R/W-0
Bit
U-0
—
FRMCNT<2:0>
x = Bit is unknown
25/17/9/1
SPIFE
R/W-0
R/W-0
R/W-0
R/W-0
SMP
Bit
SRXISEL<1:0>
ENHBUF
24/16/8/0
CKE
R/W-0
R/W-0
R/W-0
R/W-0
Bit
(3)
(2)