PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 152

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 12-1:
DS61168D-page 152
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-8
bit 7
bit 6
bit 5-4
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
ON: Timer On bit
1 = Timer is enabled
0 = Timer is disabled
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
Unimplemented: Read as ‘0’
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
Unimplemented: Read as ‘0’
TCKPS<1:0>: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
31/23/15/7
TGATE
ON
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(1)
T1CON: TYPE A TIMER CONTROL REGISTER
30/22/14/6
(1)
Bit
U-0
U-0
U-0
U-0
—
—
—
—
‘1’ = Bit is set
W = Writable bit
29/21/13/5
R/W-0
SIDL
R/W-0
Bit
U-0
U-0
—
—
TCKPS<1:0>
Preliminary
28/20/12/4
TWDIS
R/W-0
R/W-0
Bit
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
TWIP
Bit
U-0
U-0
R-0
U-0
—
—
—
26/18/10/2
TSYNC
© 2011-2012 Microchip Technology Inc.
R/W-0
Bit
U-0
U-0
U-0
—
—
—
x = Bit is unknown
25/17/9/1
R/W-0
TCS
Bit
U-0
U-0
U-0
—
—
—
24/16/8/0
Bit
U-0
U-0
U-0
U-0
—
—
—
—