ISP1760BEGA STEricsson, ISP1760BEGA Datasheet - Page 42

• Manufacturer Part Number: ISP1760BEGA
• Manufacturer: STEricsson

Specifications of ISP1760BEGA

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 37.
Table 38.
[1]
CD00222702
Product data sheet
Bit
31 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Scratch register (address 0308h) bit description
SW Reset - Software Reset register (address 030Ch) bit allocation
Symbol
SCRATCH[31:0]
8.3.3 Scratch register
8.3.4 SW Reset register
8.3.5 DMA Configuration register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
This register is for testing and debugging purposes only. The value read back must be the
same as the value that was written. The bit description of this register is given in
Table 38
Table 39.
The bit allocation of the DMA Configuration register is given in
Bit
31 to 2
1
0
Access
R/W
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
shows the bit allocation of the register.
Symbol
-
RESET_HC Reset Host Controller: Reset only the host controller-specific registers
RESET_ALL Reset All: Reset all the host controller and CPU interface registers.
SW Reset - Software Reset register (address 030Ch) bit description
Value
0000 0000h
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
reserved
Description
reserved; write logic 0
(only registers with address 300h and below).
0 — No reset
1 — Enable reset
0 — No reset
1 — Enable reset
Rev. 08 — 13 April 2010
Description
Scratch: For testing and debugging purposes
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Table
RESET_
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
40.
HC
25
17
0
0
9
0
1
0
ISP1760
RESET_
Table
R/W
R/W
R/W
R/W
ALL
42 of 105
24
16
0
0
8
0
0
0
37.