ISP1760BEGA STEricsson, ISP1760BEGA Datasheet - Page 55

• Manufacturer Part Number: ISP1760BEGA
• Manufacturer: STEricsson

Specifications of ISP1760BEGA

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CD00222702
Product data sheet
8.4.3 ISO IRQ Mask OR register
Table 62.
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
see
Bit
31 to 10
9
8
7
6
5
4
3
2
1
0
Section
Interrupt Enable register (address 0314h) bit description
7.4.
Symbol
-
ISO_IRQ_E
ATL_IRQ_E
INT_IRQ_E
CLKREADY_
E
HCSUSP_E
-
DMAEOTINT
_E
-
SOFITLINT_
E
-
Rev. 08 — 13 April 2010
Description
reserved; write logic 0
ISO IRQ Enable: Controls the IRQ assertion when one or more ISO
PTDs matching the ISO IRQ Mask AND or ISO IRQ Mask OR
register bits combination are completed.
0 — No IRQ will be asserted when ISO PTDs are completed.
1 — IRQ will be asserted.
For details, see
ATL IRQ Enable: Controls the IRQ assertion when one or more ATL
PTDs matching the ATL IRQ Mask AND or ATL IRQ Mask OR
register bits combination are completed.
0 — No IRQ will be asserted when ATL PTDs are completed.
1 — IRQ will be asserted.
For details, see
INT IRQ Enable: Controls the IRQ assertion when one or more INT
PTDs matching the INT IRQ Mask AND or INT IRQ Mask OR register
bits combination are completed.
0 — No IRQ will be asserted when INT PTDs are completed.
1 — IRQ will be asserted.
For details, see
Clock Ready Enable: Enables the IRQ assertion when internal clock
signals are running stable. Useful after wake-up.
0 — No IRQ will be generated after a CLKREADY_E event.
1 — IRQ will be generated after a CLKREADY_E event.
Host Controller Suspend Enable: Enables the IRQ generation
when the host controller enters suspend mode.
0 — No IRQ will be generated when the host controller enters
suspend mode.
1 — IRQ will be generated when the host controller enters suspend
mode.
reserved; write logic 0
DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA
transfer completion.
0 — No IRQ will be generated when a DMA transfer is completed.
1 — IRQ will be asserted when a DMA transfer is completed.
reserved; must be written with logic 0
SOT ITL Interrupt Enable: Controls the IRQ generation at every
SOF occurrence.
0 — No IRQ will be generated on an SOF occurrence.
1 — IRQ will be asserted at every SOF.
reserved; must be written with logic 0
Section
Section
Section
Embedded Hi-Speed USB host controller
7.4.
7.4.
7.4.
Table 63
for bit description. For details,
© ST-ERICSSON 2010. All rights reserved.
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