STPCC5HEBC STMicroelectronics, STPCC5HEBC Datasheet - Page 20

• Manufacturer Part Number: STPCC5HEBC
• Description: IC SYSTEM-ON-CHIP X86 388-PBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STPCC5HEBC

• Applications: Set-Top Boxes, TV
• Core Processor: x86
• Program Memory Type: External Program Memory
• Controller Series: STPC® Consumer-II
• Ram Size: External
• Interface: EBI/EMI, I²C, IDE, ISA, Local Bus
• Number Of I /o: -
• Voltage - Supply: 2.45 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Not Compliant

PIN DESCRIPTION
2.2.7. VGA CONTROLLER
RED, GREEN, BLUE RGB Video Outputs. These
are the three analog colour outputs from the
RAMDACs. These signals are sensitive to
interference, therefore they need to be properly
shielded.
VSYNC Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
HSYNC Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC DAC Voltage reference. An external
voltage reference is connected to this pin to bias
the DAC.
RSET Resistor Current Set. This reference
current input to the RAMDAC is used to set the
full-scale output of the RAMDAC.
COMP Compensation. This is the RAMDAC
compensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
V
2.2.8. VIDEO INPUT PORT
VCLK Pixel Clock Input. This signal is used to
synchronise data being transferred from an
external video device to either the frame buffer, or
alternatively out the TV output in bypass mode.
This pin can be sourced from STPC if no external
VCLK is detected, or can be input from an external
video clock source.
VIN[7:0] YUV Video Data Input CCIR 601 or 656.
Time
chrominance data as defined in ITU-R Rec601-2
and Rec656 (except for TTL input levels). This bus
typically carries a stream of Cb,Y,Cr,Y digital
video at VCLK frequency, clocked on the rising
edge (by default) of VCLK.
2.2.9. ANALOG TV OUTPUT PORT
RED_TV
synchronized with CVBS. This output is current-
driven and must be connected to analog ground
over a load resistor (R
resistor, a simple analog low pass filter is
recommended. In S-VHS mode, this is the
Chrominance Output.
GREEN_TV
synchronized with CVBS. This output is current-
driven and must be connected to analog ground
over a load resistor (R
resistor, a simple analog low pass filter is
20/93
DD
to damp oscillations.
multiplexed
/
/
C_TV
Y_TV Analog
4:2:2
LOAD
LOAD
Analog
). Following the load
). Following the load
luminance
video
video
Release 1.5 - January 29, 2002
outputs
outputs
and
recommended. In S-VHS mode, this is the
Luminance Output.
BLUE_TV
synchronized with CVBS. This output is current-
driven and must be connected to analog ground
over a load resistor (R
resistor, a simple analog low pass filter is
recommended. In S-VHS mode, this is a second
composite output.
CVBS Analog video composite output (luminance/
chrominance). CVBS is current-driven and must
be connected to analog ground over a load
resistor (R
simple analog low pass filter is recommended.
IREF1_TV Ref. current for CVBS 10-bit DAC.
IREF2_TV Reference current for RGB 10-bit DAC.
VREF1_TV Ref. voltage for CVBS 10-bit DAC.
Connect to analog ground.
VREF2_TV Reference voltage for RGB 10-bit
DAC. Connect to analog ground.
VSSA_TV Analog V
VDDA_TV Analog V
JTAG Signals
VCS Line synchronisation Output. This pin is an
input in ODDEV+HSYNC or VSYNC + HSYNC or
VSYNC slave modes and an output in all other
modes (master/slave)
ODD_EVEN Frame Synchronisation Output. This
pin supports the Frame synchronisation signal. It
is an input in slave modes, except when sync is
extracted from YCrCbdata, and an output in
master mode and when sync is extracted from
YCrCb data
The signal is synchronous to rising edge of DCLK.
The default polarity for this pin is:
- odd (not-top) field: LOW level
- even (bottom) field: HIGH level
2.2.10. MISCELLANEOUS
SPKRD Speaker Drive. This the output to the
speaker. It is an AND of the counter 2 output with
bit 1 of Port 61, and drives an external speaker
driver. This output should be connected to 7407
type high voltage driver.
SCL, SDA I²C Interface . These bidirectional pins
are connected to CRTC register 3Fh to implement
DDC capabilities. They conform to I
specifications, they have open-collector output
drivers which are internally connected to V
through pull-up resistors.
LOAD
/
CVBS
). Following the load resistor, a
SS
DD
for DACs.
LOAD
for DACs.
Analog
). Following the load
video
2
C electrical
outputs
DD