STPCC5HEBC STMicroelectronics, STPCC5HEBC Datasheet - Page 40
STPCC5HEBC
Manufacturer Part Number
STPCC5HEBC
Description
IC SYSTEM-ON-CHIP X86 388-PBGA
Manufacturer
STMicroelectronics
Series
-r
Datasheet
1.STPCC5HEBC.pdf
(93 pages)
Specifications of STPCC5HEBC
Applications
Set-Top Boxes, TV
Core Processor
x86
Program Memory Type
External Program Memory
Controller Series
STPC® Consumer-II
Ram Size
External
Interface
EBI/EMI, I²C, IDE, ISA, Local Bus
Number Of I /o
-
Voltage - Supply
2.45 V ~ 3.6 V
Operating Temperature
0°C ~ 85°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Not Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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ELECTRICAL SPECIFICATIONS
4.5.3. SDRAM INTERFACE
Figure
of the SDRAM interface.
Table 4-10. SDRAM Bus AC Timing
For correct operation, the programmable read
clock delay (RDCLK) must be activated for the
CRTC and the delay set to the minimum. This is
done by setting the Latch_CRTC_Data_In bit in
the SDRAM Controller register 0 and clear the
bits[3:0] in register 1.
40/93
Note: These timing are for a load of 50pF.
Toutput
Tsetup
Tdelay
Tcycle
MCLKx
MCLKI
STPC.output
STPC.input
Name
Thigh
Thold
Tlow
4-5,
Table 4-10
Parameter
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
MCLKx to MCLKI delay
MCLKI to Outputs Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MD[63:0] setup to MCKLI
MD[63:0] hold from MCKLI
lists the AC characteristics
T
hold
T
delay
Figure 4-5. SDRAM Timing Diagram
Release 1.5 - January 29, 2002
T
output (max)
T
high
The PC133 memory is recommended to reach
100MHz operation.
T
cycle
T
setup
T
T
output (min)
low
3.75
Min
5.2
6.5
6.5
1.3
10
4
4
Typ
-0.9
Max
8.8
8.8
4.0
2.5
1
1
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns