82V3280EQG IDT, Integrated Device Technology Inc, 82V3280EQG Datasheet - Page 143

• Manufacturer Part Number: 82V3280EQG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3280EQG

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

OUT8_FREQ_CNFG - Output Clock 8 Frequency Configuration & Output Clock 6, 7 & 9 Invert Configuration
Programming Information
IDT82V3280
Address:72H
Type: Read / Write
Default Value: 01000000
OUT8_PATH_S
Bit
7
6
5
4
3
2
1
0
EL
7
OUT8_PATH_SEL
AMI_OUT_DUTY
T4_INPUT_FAIL
400HZ_SEL
OUT9_INV
OUT7_INV
OUT6_INV
OUT8_EN
Name
OUT8_EN
6
These bits select an input to OUT8.
0: The output of T4 DPLL 77.76 MHz path. (default)
1: The output of T0 DPLL 77.76 MHz path.
Refer to the description of the T4_INPUT_FAIL bit (b5, 72H).
This bit, together with the OUT8_EN bit (b6, 72H), determines whether a clock is enabled to be output on OUT8.
This bit determines the duty cycle of the output on OUT8.
0: 50:50. (default)
1: 5:8.
This bit determines the frequency of the output on OUT8.
0: 64 kHz + 8 kHz. (default)
1: 64 kHz + 8 kHz + 0.4 kHz.
This bit determines whether the output on OUT9 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT7 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT6 is inverted.
0: Not inverted. (default)
1: Inverted.
OUT8_EN T4_INPUT_FAIL
T4_INPUT_FAI
0
1
5
L
don’t-care
0
1
AMI_OUT_DUT
Y
4
143
Output is disabled (output low) when the T4 selected input clock fails.
Output is enabled when the T4 selected input clock does not fail.
400HZ_SEL
3
Description
Output is disabled (output low).
Output is enabled. (default)
OUT9_INV
Output on OUT8
2
OUT7_INV
1
December 9, 2008
OUT6_INV
0
WAN PLL