82V3280EQG IDT, Integrated Device Technology Inc, 82V3280EQG Datasheet - Page 23

• Manufacturer Part Number: 82V3280EQG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3280EQG

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.5
lowing aspects:
quency monitoring are conducted on all the input clocks.
and T4 selected input clocks have to be monitored further. Refer to
Chapter 3.7 Selected Input Clock Monitoring
3.5.1
ducted on IN1 and IN2. A LOS event occurs when the amplitude of the
input clock falls below +0.6 Vp-p for 1 ms; the LOS event is cleared
when the amplitude rises higher than +1 Vp-p.
AMI1_LOS
an interrupt.
T4 DPLL.
3.5.2
as shown in
Functional Description
IDT82V3280
Leaky Bucket Accumulator
The qualities of all the input clocks are always monitored in the fol-
LOS monitoring is only conducted on IN1 and IN2. Activity and fre-
The qualified clocks are available for T0/T4 DPLL selection. The T0
IN1 and IN2 support the AMI input signal. LOS monitoring is con-
LOS status is indicated by the AMI1_LOS
The input clock in LOS status is disqualified for clock selection for T0/
Activity is monitored by using an internal leaky bucket accumulator,
No-activity Alarm Indication
• LOS (loss of signal) (only for IN1 and IN2)
• Activity
• Frequency
Input Clock
INPUT CLOCK QUALITY MONITORING
LOS MONITORING
2
ACTIVITY MONITORING
Figure
/ AMI2_LOS
4.
2
bit is ‘1’, the occurrence of LOS will trigger
clock signal with no event
for details.
1
Figure 4. Input Clock Activity Monitoring
/ AMI2_LOS
Decay
Rate
1
bit. If the
23
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
The leaky bucket configuration for an input clock is selected by the cor-
responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
the accumulated events reach the bucket size, the accumulator will stop
increasing even if further events are detected. The upper threshold is a
point above which a no-activity alarm is raised. The lower threshold is a
point below which the no-activity alarm is cleared. The decay rate is a
certain period during which the accumulator decreases by 1 if no event
is detected.
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0]
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 0 ~ 3.
INn_NO_ACTIVITY_ALARM bit (14 ≥ n ≥ 1).
tion for T0/T4 DPLL.
clock signal with events
Each input clock is assigned an internal leaky bucket accumulator.
There are four configurations (0 - 3) for a leaky bucket accumulator.
The bucket size is the capability of the accumulator. If the number of
The leaky bucket configuration is programmed by one of four groups
The no-activity alarm status of the input clock is indicated by the
The input clock with a no-activity alarm is disqualified for clock selec-
bits,
the
LOWER_THRESHOLD_n_
December 9, 2008
Bucket Size
Upper Threshold
Lower Threshold
0
WAN PLL