82V3280EQG IDT, Integrated Device Technology Inc, 82V3280EQG Datasheet - Page 78

• Manufacturer Part Number: 82V3280EQG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3280EQG

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3
Programming Information
IDT82V3280
Address: 12H
Type: Read / Write
Default Value: 00X00000
EX_SYNC_ALARM
Bit
7
6
5
4
3
2
1
0
7
EX_SYNC_ALARM
INPUT_TO_T4
AMI2_VIOL
AMI1_VIOL
AMI2_LOS
AMI1_LOS
T4_STS
Name
-
T4_STS
6
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has
occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T4 DPLL locking status
changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’), i.e., when the T4_STS bit (b6, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when all the input clocks for T4 path
change to be unqualified, i.e., when the INPUT_TO_T4 bit (b4, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN2 has AMI violation, i.e., when the
AMI2_VIOL bit (b3, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN2 has LOS error, i.e., when the
AMI2_LOS bit (b2, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN1 has AMI violation, i.e., when the
AMI1_VIOL bit (b1, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN1 has LOS error, i.e., when the
AMI1_LOS bit (b0, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
5
-
INPUT_TO_T4
4
78
AMI2_VIOL
3
Description
AMI2_LOS
2
AMI1_VIOL
1
December 9, 2008
AMI1_LOS
0
WAN PLL