82V3280EQG IDT, Integrated Device Technology Inc, 82V3280EQG Datasheet - Page 5

• Manufacturer Part Number: 82V3280EQG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3280EQG

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table of Contents
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 151
PACKAGE DIMENSIONS.................................................................................................................................................... 168
ORDERING INFORMATION................................................................................................................................................ 171
IDT82V3280
8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 149
8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 149
8.4 TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 150
9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 151
9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 151
9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 152
9.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 158
9.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 161
9.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 162
9.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 163
9.3.1
9.3.2
9.3.3
AMI Input / Output Port ................................................................................................................................................................ 152
9.3.1.1
9.3.1.2
9.3.1.3
CMOS Input / Output Port ............................................................................................................................................................ 154
PECL / LVDS Input / Output Port ................................................................................................................................................ 155
9.3.3.1
9.3.3.2
Structure ......................................................................................................................................................................... 152
I/O Level ......................................................................................................................................................................... 152
Over-Voltage Protection ................................................................................................................................................. 154
PECL Input / Output Port ................................................................................................................................................ 155
LVDS Input / Output Port ................................................................................................................................................ 157
5
December 9, 2008
WAN PLL