82V3280EQG IDT, Integrated Device Technology Inc, 82V3280EQG Datasheet - Page 79

• Manufacturer Part Number: 82V3280EQG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3280EQG

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

7.2.3
IN1_CNFG - Input Clock 1 Configuration
IN2_CNFG - Input Clock 2 Configuration
Programming Information
IDT82V3280
Address: 14H
Type: Read / Write
Default Value: X0000000
Address: 15H
Type: Read / Write
Default Value: X0000000
5 - 4
3 - 0
Bit
5 - 4
3 - 0
7
6
Bit
7
6
7
7
-
-
INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
IN_FREQ[3:0]
400HZ_SEL
IN_FREQ[3:0]
400HZ_SEL
Name
Name
400HZ_SEL
-
400HZ_SEL
-
6
6
Reserved.
This bit should be set to match the clock input on IN1:
0: 64 kHz + 8 kHz. (default)
1: 64 kHz + 8 kHz + 0.4 kHz.
These bits select one of the four groups of leaky bucket configuration registers for IN1:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN1:
0000: 8 kHz. (default)
0001 ~ 1111: Reserved.
Reserved.
This bit should be set to match the clock input on IN2:
0: 64 kHz + 8 kHz. (default)
1: 64 kHz + 8 kHz + 0.4 kHz.
These bits select one of the four groups of leaky bucket configuration registers for IN2:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN2:
0000: 8 kHz. (default)
0001 ~ 1111: Reserved.
BUCKET_SEL1
BUCKET_SEL1
5
5
BUCKET_SEL0
BUCKET_SEL0
4
4
79
IN_FREQ3
IN_FREQ3
3
3
Description
Description
IN_FREQ2
IN_FREQ2
2
2
IN_FREQ1
IN_FREQ1
1
1
December 9, 2008
IN_FREQ0
IN_FREQ0
0
0
WAN PLL