AD9548BCPZ Analog Devices Inc, AD9548BCPZ Datasheet - Page 77

IC CLOCK GEN/SYNCHRONIZR 88LFCSP

AD9548BCPZ

Manufacturer Part Number
AD9548BCPZ
Description
IC CLOCK GEN/SYNCHRONIZR 88LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9548BCPZ

Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
88-LFCSP
Frequency-max
*
Clock Ic Type
Clock Synthesizer
Ic Interface Type
Serial
Frequency
1GHz
No. Of Outputs
4
No. Of Multipliers / Dividers
4
Supply Current
190mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0400 TO REGISTER 0419)
Table 65. Distribution Settings
Address
0400
1
Table 66. Distribution Enable
Address
0401
When Bits[3:0] = 1111, the clock distribution output enters a deep sleep mode.
[7:6]
[5]
[4]
[3]
[2]
[1]
[0]
Bits
[7:4]
[3]
[2]
[1]
[0]
Bits
Bit Name
Unused
External distribution
resistor
Receiver mode
OUT3 power-down
OUT2 power-down
OUT1 power-down
OUT0 power-down
Bit Name
Unused
OUT3 enable
OUT2 enable
OUT1 enable
OUT0 enable
1
Description
Enable the OUT3 driver.
0 (default) = disable.
1 = enable.
Enable the OUT2 driver.
0 (default) = disable.
1 = enable.
Enable the OUT1 driver.
0 (default) = disable.
1 = enable.
Enable the OUT0 driver.
0 (default) = disable.
1 = enable.
Description
Output current control for the clock distribution outputs
0 (default) = internal current setting resistor
1 = external current setting resistor
Clock distribution receiver mode
0 (default) = normal operation
1 = high frequency mode (super-Nyquist)
Power-down clock distribution output OUT3
0 (default) = normal operation
1 = power-down
Power-down clock distribution output OUT2
0 (default) = normal operation
1 = power-down
Power-down clock distribution output OUT1
0 (default) = normal operation
1 = power-down
Power-down clock distribution output OUT0
0 (default) = normal operation
1 = power-down
Rev. A | Page 77 of 112
AD9548

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