MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 5

417/333/233 MP Std Tmp

MPC8309VMAHFCA

Manufacturer Part Number
MPC8309VMAHFCA
Description
417/333/233 MP Std Tmp
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8309VMAHFCA

Processor Series
MPC8309
Core
e300c3
Data Bus Width
32 bit
Data Ram Size
512 MB
Interface Type
USB, CAN, UART, PCI
Maximum Clock Frequency
417 MHz
Number Of Programmable I/os
56
Operating Supply Voltage
- 0.3 V to + 1.26 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
0 C to + 105 C
Processor To Be Evaluated
MPC8309
Supply Current (max)
5 uA
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8309VMAHFCA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
— Six groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Unique vector number for each interrupt source
PCI interface
— Designed to comply with PCI Local Bus Specification, Revision 2.3
— 32-bit PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— Not 5-V compatible
— Support for host and agent modes
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting three masters on PCI
— Arbiter support for two-level priority request/grant signal pairs
— Support for accesses to all PCI address spaces
— Support for parity
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Mapping from an external 32-/64-bit address space to the internal 32-bit local space
— Support for dual address cycle (DAC) (as a target only)
— Internal configuration registers accessible from PCI
— Selectable snooping for inbound transactions
— Four outbound Translation Address Windows
— Four inbound Translation Address Windows corresponding to defined PCI BARs
Enhanced secure digital host controller (eSDHC)
— Compatible with the SD Host Controller Standard Specification Version 2.0 with test event
— Compatible with the MMC System Specification Version 4.2
— Compatible with the SD Memory Card Specification Version 2.0 and supports the high capacity
— Compatible with the SD Input/Output (SDIO) Card Specification, Version 2.0
— Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
– Support for mapping 32-bit internal local memory space to an external 32-bit PCI address
– The first BAR is 32-bits and dedicated to on-chip register access
– The second BAR is 32-bits for general use
– The remaining two BARs may be 32- or 64-bits and are also for general use
register support
SD memory card
MMCplus, and RS-MMC cards
space and translating that address within the PCI space
Overview
5

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