MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 75

• Manufacturer Part Number: MPC8309VMAHFCA
• Description: 417/333/233 MP Std Tmp
• Manufacturer: Freescale Semiconductor

Specifications of MPC8309VMAHFCA

• Processor Series: MPC8309
• Core: e300c3
• Data Bus Width: 32 bit
• Data Ram Size: 512 MB
• Interface Type: USB, CAN, UART, PCI
• Maximum Clock Frequency: 417 MHz
• Number Of Programmable I/os: 56
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 105 C
• Processor To Be Evaluated: MPC8309
• Supply Current (max): 5 uA
• Lead Free Status / Rohs Status: Details

lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.
If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic
surfaces and its performance verified under the application requirements.
24.2.1
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface.
From this case temperature, the junction temperature is determined from the junction-to-case thermal
resistance using the following equation:
where:
25 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8309.
25.1
The MPC8309 includes three PLLs.
Freescale Semiconductor
•
•
•
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
T
R
P
The system PLL (AV
input. The frequency ratio between the system and SYS_CLK_IN is selected using the system PLL
ratio configuration bits as described in
The e300 core PLL (AV
ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio
configuration bits as described in
The QUICC Engine PLL (AV
Engine block generates or uses external sources for all required serial interface clocks.
C

D
System Clocking
JC
= case temperature of the package (C)
= power dissipation (W)
Experimental Determination of the Junction Temperature with a
Heat Sink
= junction-to-case thermal resistance (C/W)
DD2
DD3
)
generates the system clock from the externally supplied SYS_CLK_IN
)
generates the core clock as a slave to the system clock. The frequency
DD1
T
J
)
Section 23.5, “Core PLL Configuration.”
which uses the same reference as the system PLL. The QUICC
= T
C
Section 23.4, “System PLL Configuration.”
+ (R

JC
 P
D
)
System Design Information
Eqn. 5
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